#ifndef INCLUDED_CYFITTER_H
#define INCLUDED_CYFITTER_H
#include "cydevice_trm.h"

/* Gain */
#define Gain__0__DR CYREG_GPIO_PRT2_DR
#define Gain__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Gain__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Gain__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Gain__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Gain__0__HSIOM_MASK 0x000F0000u
#define Gain__0__HSIOM_SHIFT 16u
#define Gain__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Gain__0__INTR CYREG_GPIO_PRT2_INTR
#define Gain__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Gain__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define Gain__0__MASK 0x10u
#define Gain__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Gain__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Gain__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Gain__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Gain__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Gain__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Gain__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Gain__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Gain__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Gain__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Gain__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Gain__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Gain__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Gain__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Gain__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Gain__0__PC CYREG_GPIO_PRT2_PC
#define Gain__0__PC2 CYREG_GPIO_PRT2_PC2
#define Gain__0__PORT 2u
#define Gain__0__PS CYREG_GPIO_PRT2_PS
#define Gain__0__SHIFT 4
#define Gain__DR CYREG_GPIO_PRT2_DR
#define Gain__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Gain__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Gain__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Gain__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Gain__INTR CYREG_GPIO_PRT2_INTR
#define Gain__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Gain__INTSTAT CYREG_GPIO_PRT2_INTR
#define Gain__MASK 0x10u
#define Gain__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Gain__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Gain__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Gain__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Gain__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Gain__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Gain__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Gain__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Gain__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Gain__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Gain__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Gain__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Gain__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Gain__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Gain__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Gain__PC CYREG_GPIO_PRT2_PC
#define Gain__PC2 CYREG_GPIO_PRT2_PC2
#define Gain__PORT 2u
#define Gain__PS CYREG_GPIO_PRT2_PS
#define Gain__SHIFT 4

/* A_out */
#define A_out__0__DR CYREG_GPIO_PRT2_DR
#define A_out__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define A_out__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define A_out__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define A_out__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define A_out__0__HSIOM_MASK 0x0000F000u
#define A_out__0__HSIOM_SHIFT 12u
#define A_out__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define A_out__0__INTR CYREG_GPIO_PRT2_INTR
#define A_out__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define A_out__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define A_out__0__MASK 0x08u
#define A_out__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define A_out__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define A_out__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define A_out__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define A_out__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define A_out__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define A_out__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define A_out__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define A_out__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define A_out__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define A_out__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define A_out__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define A_out__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define A_out__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define A_out__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define A_out__0__PC CYREG_GPIO_PRT2_PC
#define A_out__0__PC2 CYREG_GPIO_PRT2_PC2
#define A_out__0__PORT 2u
#define A_out__0__PS CYREG_GPIO_PRT2_PS
#define A_out__0__SHIFT 3
#define A_out__DR CYREG_GPIO_PRT2_DR
#define A_out__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define A_out__DR_INV CYREG_GPIO_PRT2_DR_INV
#define A_out__DR_SET CYREG_GPIO_PRT2_DR_SET
#define A_out__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define A_out__INTR CYREG_GPIO_PRT2_INTR
#define A_out__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define A_out__INTSTAT CYREG_GPIO_PRT2_INTR
#define A_out__MASK 0x08u
#define A_out__PA__CFG0 CYREG_UDB_PA2_CFG0
#define A_out__PA__CFG1 CYREG_UDB_PA2_CFG1
#define A_out__PA__CFG10 CYREG_UDB_PA2_CFG10
#define A_out__PA__CFG11 CYREG_UDB_PA2_CFG11
#define A_out__PA__CFG12 CYREG_UDB_PA2_CFG12
#define A_out__PA__CFG13 CYREG_UDB_PA2_CFG13
#define A_out__PA__CFG14 CYREG_UDB_PA2_CFG14
#define A_out__PA__CFG2 CYREG_UDB_PA2_CFG2
#define A_out__PA__CFG3 CYREG_UDB_PA2_CFG3
#define A_out__PA__CFG4 CYREG_UDB_PA2_CFG4
#define A_out__PA__CFG5 CYREG_UDB_PA2_CFG5
#define A_out__PA__CFG6 CYREG_UDB_PA2_CFG6
#define A_out__PA__CFG7 CYREG_UDB_PA2_CFG7
#define A_out__PA__CFG8 CYREG_UDB_PA2_CFG8
#define A_out__PA__CFG9 CYREG_UDB_PA2_CFG9
#define A_out__PC CYREG_GPIO_PRT2_PC
#define A_out__PC2 CYREG_GPIO_PRT2_PC2
#define A_out__PORT 2u
#define A_out__PS CYREG_GPIO_PRT2_PS
#define A_out__SHIFT 3

/* CyBle_bless_isr */
#define CyBle_bless_isr__INTC_CLR_EN_REG CYREG_CM0_ICER
#define CyBle_bless_isr__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define CyBle_bless_isr__INTC_MASK 0x1000u
#define CyBle_bless_isr__INTC_NUMBER 12u
#define CyBle_bless_isr__INTC_PRIOR_MASK 0xC0u
#define CyBle_bless_isr__INTC_PRIOR_NUM 2u
#define CyBle_bless_isr__INTC_PRIOR_REG CYREG_CM0_IPR3
#define CyBle_bless_isr__INTC_SET_EN_REG CYREG_CM0_ISER
#define CyBle_bless_isr__INTC_SET_PD_REG CYREG_CM0_ISPR

/* CyBle_cy_m0s8_ble */
#define CyBle_cy_m0s8_ble__ADC_BUMP1 CYREG_BLE_BLERD_ADC_BUMP1
#define CyBle_cy_m0s8_ble__ADC_BUMP2 CYREG_BLE_BLERD_ADC_BUMP2
#define CyBle_cy_m0s8_ble__ADV_CH_TX_POWER CYREG_BLE_BLELL_ADV_CH_TX_POWER
#define CyBle_cy_m0s8_ble__ADV_CONFIG CYREG_BLE_BLELL_ADV_CONFIG
#define CyBle_cy_m0s8_ble__ADV_INTERVAL_TIMEOUT CYREG_BLE_BLELL_ADV_INTERVAL_TIMEOUT
#define CyBle_cy_m0s8_ble__ADV_INTR CYREG_BLE_BLELL_ADV_INTR
#define CyBle_cy_m0s8_ble__ADV_NEXT_INSTANT CYREG_BLE_BLELL_ADV_NEXT_INSTANT
#define CyBle_cy_m0s8_ble__ADV_PARAMS CYREG_BLE_BLELL_ADV_PARAMS
#define CyBle_cy_m0s8_ble__ADV_SCN_RSP_TX_FIFO CYREG_BLE_BLELL_ADV_SCN_RSP_TX_FIFO
#define CyBle_cy_m0s8_ble__ADV_TX_DATA_FIFO CYREG_BLE_BLELL_ADV_TX_DATA_FIFO
#define CyBle_cy_m0s8_ble__AGC CYREG_BLE_BLERD_AGC
#define CyBle_cy_m0s8_ble__BALUN CYREG_BLE_BLERD_BALUN
#define CyBle_cy_m0s8_ble__BB_BUMP1 CYREG_BLE_BLERD_BB_BUMP1
#define CyBle_cy_m0s8_ble__BB_BUMP2 CYREG_BLE_BLERD_BB_BUMP2
#define CyBle_cy_m0s8_ble__BB_XO CYREG_BLE_BLERD_BB_XO
#define CyBle_cy_m0s8_ble__BB_XO_CAPTRIM CYREG_BLE_BLERD_BB_XO_CAPTRIM
#define CyBle_cy_m0s8_ble__CE_CNFG_STS_REGISTER CYREG_BLE_BLELL_CE_CNFG_STS_REGISTER
#define CyBle_cy_m0s8_ble__CE_LENGTH CYREG_BLE_BLELL_CE_LENGTH
#define CyBle_cy_m0s8_ble__CFG_1_FCAL CYREG_BLE_BLERD_CFG_1_FCAL
#define CyBle_cy_m0s8_ble__CFG_2_FCAL CYREG_BLE_BLERD_CFG_2_FCAL
#define CyBle_cy_m0s8_ble__CFG_3_FCAL CYREG_BLE_BLERD_CFG_3_FCAL
#define CyBle_cy_m0s8_ble__CFG_4_FCAL CYREG_BLE_BLERD_CFG_4_FCAL
#define CyBle_cy_m0s8_ble__CFG_5_FCAL CYREG_BLE_BLERD_CFG_5_FCAL
#define CyBle_cy_m0s8_ble__CFG_6_FCAL CYREG_BLE_BLERD_CFG_6_FCAL
#define CyBle_cy_m0s8_ble__CFG1 CYREG_BLE_BLERD_CFG1
#define CyBle_cy_m0s8_ble__CFG2 CYREG_BLE_BLERD_CFG2
#define CyBle_cy_m0s8_ble__CFGCTRL CYREG_BLE_BLERD_CFGCTRL
#define CyBle_cy_m0s8_ble__CLOCK_CONFIG CYREG_BLE_BLELL_CLOCK_CONFIG
#define CyBle_cy_m0s8_ble__COMMAND_REGISTER CYREG_BLE_BLELL_COMMAND_REGISTER
#define CyBle_cy_m0s8_ble__CONN_CE_COUNTER CYREG_BLE_BLELL_CONN_CE_COUNTER
#define CyBle_cy_m0s8_ble__CONN_CE_INSTANT CYREG_BLE_BLELL_CONN_CE_INSTANT
#define CyBle_cy_m0s8_ble__CONN_CH_TX_POWER CYREG_BLE_BLELL_CONN_CH_TX_POWER
#define CyBle_cy_m0s8_ble__CONN_CONFIG CYREG_BLE_BLELL_CONN_CONFIG
#define CyBle_cy_m0s8_ble__CONN_INDEX CYREG_BLE_BLELL_CONN_INDEX
#define CyBle_cy_m0s8_ble__CONN_INTERVAL CYREG_BLE_BLELL_CONN_INTERVAL
#define CyBle_cy_m0s8_ble__CONN_INTR CYREG_BLE_BLELL_CONN_INTR
#define CyBle_cy_m0s8_ble__CONN_INTR_MASK CYREG_BLE_BLELL_CONN_INTR_MASK
#define CyBle_cy_m0s8_ble__CONN_PARAM1 CYREG_BLE_BLELL_CONN_PARAM1
#define CyBle_cy_m0s8_ble__CONN_PARAM2 CYREG_BLE_BLELL_CONN_PARAM2
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD0 CYREG_BLE_BLELL_CONN_REQ_WORD0
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD1 CYREG_BLE_BLELL_CONN_REQ_WORD1
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD10 CYREG_BLE_BLELL_CONN_REQ_WORD10
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD11 CYREG_BLE_BLELL_CONN_REQ_WORD11
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD2 CYREG_BLE_BLELL_CONN_REQ_WORD2
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD3 CYREG_BLE_BLELL_CONN_REQ_WORD3
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD4 CYREG_BLE_BLELL_CONN_REQ_WORD4
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD5 CYREG_BLE_BLELL_CONN_REQ_WORD5
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD6 CYREG_BLE_BLELL_CONN_REQ_WORD6
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD7 CYREG_BLE_BLELL_CONN_REQ_WORD7
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD8 CYREG_BLE_BLELL_CONN_REQ_WORD8
#define CyBle_cy_m0s8_ble__CONN_REQ_WORD9 CYREG_BLE_BLELL_CONN_REQ_WORD9
#define CyBle_cy_m0s8_ble__CONN_RXMEM_BASE_ADDR CYREG_BLE_BLELL_CONN_RXMEM_BASE_ADDR
#define CyBle_cy_m0s8_ble__CONN_STATUS CYREG_BLE_BLELL_CONN_STATUS
#define CyBle_cy_m0s8_ble__CONN_TXMEM_BASE_ADDR CYREG_BLE_BLELL_CONN_TXMEM_BASE_ADDR
#define CyBle_cy_m0s8_ble__CONN_UPDATE_NEW_INTERVAL CYREG_BLE_BLELL_CONN_UPDATE_NEW_INTERVAL
#define CyBle_cy_m0s8_ble__CONN_UPDATE_NEW_LATENCY CYREG_BLE_BLELL_CONN_UPDATE_NEW_LATENCY
#define CyBle_cy_m0s8_ble__CONN_UPDATE_NEW_SL_INTERVAL CYREG_BLE_BLELL_CONN_UPDATE_NEW_SL_INTERVAL
#define CyBle_cy_m0s8_ble__CONN_UPDATE_NEW_SUP_TO CYREG_BLE_BLELL_CONN_UPDATE_NEW_SUP_TO
#define CyBle_cy_m0s8_ble__CTR1 CYREG_BLE_BLERD_CTR1
#define CyBle_cy_m0s8_ble__DATA_CHANNELS_H0 CYREG_BLE_BLELL_DATA_CHANNELS_H0
#define CyBle_cy_m0s8_ble__DATA_CHANNELS_H1 CYREG_BLE_BLELL_DATA_CHANNELS_H1
#define CyBle_cy_m0s8_ble__DATA_CHANNELS_L0 CYREG_BLE_BLELL_DATA_CHANNELS_L0
#define CyBle_cy_m0s8_ble__DATA_CHANNELS_L1 CYREG_BLE_BLELL_DATA_CHANNELS_L1
#define CyBle_cy_m0s8_ble__DATA_CHANNELS_M0 CYREG_BLE_BLELL_DATA_CHANNELS_M0
#define CyBle_cy_m0s8_ble__DATA_CHANNELS_M1 CYREG_BLE_BLELL_DATA_CHANNELS_M1
#define CyBle_cy_m0s8_ble__DATA_LIST_ACK_UPDATE__STATUS CYREG_BLE_BLELL_DATA_LIST_ACK_UPDATE__STATUS
#define CyBle_cy_m0s8_ble__DATA_LIST_SENT_UPDATE__STATUS CYREG_BLE_BLELL_DATA_LIST_SENT_UPDATE__STATUS
#define CyBle_cy_m0s8_ble__DATA_MEM_DESCRIPTOR0 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR0
#define CyBle_cy_m0s8_ble__DATA_MEM_DESCRIPTOR1 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR1
#define CyBle_cy_m0s8_ble__DATA_MEM_DESCRIPTOR2 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR2
#define CyBle_cy_m0s8_ble__DATA_MEM_DESCRIPTOR3 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR3
#define CyBle_cy_m0s8_ble__DATA_MEM_DESCRIPTOR4 CYREG_BLE_BLELL_DATA_MEM_DESCRIPTOR4
#define CyBle_cy_m0s8_ble__DATA0 CYREG_BLE_BLELL_DATA0
#define CyBle_cy_m0s8_ble__DATA1 CYREG_BLE_BLELL_DATA1
#define CyBle_cy_m0s8_ble__DATA10 CYREG_BLE_BLELL_DATA10
#define CyBle_cy_m0s8_ble__DATA11 CYREG_BLE_BLELL_DATA11
#define CyBle_cy_m0s8_ble__DATA12 CYREG_BLE_BLELL_DATA12
#define CyBle_cy_m0s8_ble__DATA13 CYREG_BLE_BLELL_DATA13
#define CyBle_cy_m0s8_ble__DATA2 CYREG_BLE_BLELL_DATA2
#define CyBle_cy_m0s8_ble__DATA3 CYREG_BLE_BLELL_DATA3
#define CyBle_cy_m0s8_ble__DATA4 CYREG_BLE_BLELL_DATA4
#define CyBle_cy_m0s8_ble__DATA5 CYREG_BLE_BLELL_DATA5
#define CyBle_cy_m0s8_ble__DATA6 CYREG_BLE_BLELL_DATA6
#define CyBle_cy_m0s8_ble__DATA7 CYREG_BLE_BLELL_DATA7
#define CyBle_cy_m0s8_ble__DATA8 CYREG_BLE_BLELL_DATA8
#define CyBle_cy_m0s8_ble__DATA9 CYREG_BLE_BLELL_DATA9
#define CyBle_cy_m0s8_ble__DBG_1 CYREG_BLE_BLERD_DBG_1
#define CyBle_cy_m0s8_ble__DBG_2 CYREG_BLE_BLERD_DBG_2
#define CyBle_cy_m0s8_ble__DBG_3 CYREG_BLE_BLERD_DBG_3
#define CyBle_cy_m0s8_ble__DBG_BB CYREG_BLE_BLERD_DBG_BB
#define CyBle_cy_m0s8_ble__DBUS CYREG_BLE_BLERD_DBUS
#define CyBle_cy_m0s8_ble__DC CYREG_BLE_BLERD_DC
#define CyBle_cy_m0s8_ble__DCCAL CYREG_BLE_BLERD_DCCAL
#define CyBle_cy_m0s8_ble__DEV_PUB_ADDR_H CYREG_BLE_BLELL_DEV_PUB_ADDR_H
#define CyBle_cy_m0s8_ble__DEV_PUB_ADDR_L CYREG_BLE_BLELL_DEV_PUB_ADDR_L
#define CyBle_cy_m0s8_ble__DEV_PUB_ADDR_M CYREG_BLE_BLELL_DEV_PUB_ADDR_M
#define CyBle_cy_m0s8_ble__DEVICE_RAND_ADDR_H CYREG_BLE_BLELL_DEVICE_RAND_ADDR_H
#define CyBle_cy_m0s8_ble__DEVICE_RAND_ADDR_L CYREG_BLE_BLELL_DEVICE_RAND_ADDR_L
#define CyBle_cy_m0s8_ble__DEVICE_RAND_ADDR_M CYREG_BLE_BLELL_DEVICE_RAND_ADDR_M
#define CyBle_cy_m0s8_ble__DIAG1 CYREG_BLE_BLERD_DIAG1
#define CyBle_cy_m0s8_ble__DPLL_CONFIG CYREG_BLE_BLELL_DPLL_CONFIG
#define CyBle_cy_m0s8_ble__DSM1 CYREG_BLE_BLERD_DSM1
#define CyBle_cy_m0s8_ble__DSM2 CYREG_BLE_BLERD_DSM2
#define CyBle_cy_m0s8_ble__DSM3 CYREG_BLE_BLERD_DSM3
#define CyBle_cy_m0s8_ble__DSM4 CYREG_BLE_BLERD_DSM4
#define CyBle_cy_m0s8_ble__DSM5 CYREG_BLE_BLERD_DSM5
#define CyBle_cy_m0s8_ble__DSM6 CYREG_BLE_BLERD_DSM6
#define CyBle_cy_m0s8_ble__DTM_RX_PKT_COUNT CYREG_BLE_BLELL_DTM_RX_PKT_COUNT
#define CyBle_cy_m0s8_ble__ENC_CONFIG CYREG_BLE_BLELL_ENC_CONFIG
#define CyBle_cy_m0s8_ble__ENC_INTR CYREG_BLE_BLELL_ENC_INTR
#define CyBle_cy_m0s8_ble__ENC_INTR_EN CYREG_BLE_BLELL_ENC_INTR_EN
#define CyBle_cy_m0s8_ble__ENC_KEY0 CYREG_BLE_BLELL_ENC_KEY0
#define CyBle_cy_m0s8_ble__ENC_KEY1 CYREG_BLE_BLELL_ENC_KEY1
#define CyBle_cy_m0s8_ble__ENC_KEY2 CYREG_BLE_BLELL_ENC_KEY2
#define CyBle_cy_m0s8_ble__ENC_KEY3 CYREG_BLE_BLELL_ENC_KEY3
#define CyBle_cy_m0s8_ble__ENC_KEY4 CYREG_BLE_BLELL_ENC_KEY4
#define CyBle_cy_m0s8_ble__ENC_KEY5 CYREG_BLE_BLELL_ENC_KEY5
#define CyBle_cy_m0s8_ble__ENC_KEY6 CYREG_BLE_BLELL_ENC_KEY6
#define CyBle_cy_m0s8_ble__ENC_KEY7 CYREG_BLE_BLELL_ENC_KEY7
#define CyBle_cy_m0s8_ble__ENC_PARAMS CYREG_BLE_BLELL_ENC_PARAMS
#define CyBle_cy_m0s8_ble__EVENT_ENABLE CYREG_BLE_BLELL_EVENT_ENABLE
#define CyBle_cy_m0s8_ble__EVENT_INTR CYREG_BLE_BLELL_EVENT_INTR
#define CyBle_cy_m0s8_ble__FCAL_TEST CYREG_BLE_BLERD_FCAL_TEST
#define CyBle_cy_m0s8_ble__FPD_TEST CYREG_BLE_BLERD_FPD_TEST
#define CyBle_cy_m0s8_ble__FSM CYREG_BLE_BLERD_FSM
#define CyBle_cy_m0s8_ble__IM CYREG_BLE_BLERD_IM
#define CyBle_cy_m0s8_ble__INIT_CONFIG CYREG_BLE_BLELL_INIT_CONFIG
#define CyBle_cy_m0s8_ble__INIT_INTERVAL CYREG_BLE_BLELL_INIT_INTERVAL
#define CyBle_cy_m0s8_ble__INIT_INTR CYREG_BLE_BLELL_INIT_INTR
#define CyBle_cy_m0s8_ble__INIT_NEXT_INSTANT CYREG_BLE_BLELL_INIT_NEXT_INSTANT
#define CyBle_cy_m0s8_ble__INIT_PARAM CYREG_BLE_BLELL_INIT_PARAM
#define CyBle_cy_m0s8_ble__INIT_SCN_ADV_RX_FIFO CYREG_BLE_BLELL_INIT_SCN_ADV_RX_FIFO
#define CyBle_cy_m0s8_ble__INIT_WINDOW CYREG_BLE_BLELL_INIT_WINDOW
#define CyBle_cy_m0s8_ble__IQMIS CYREG_BLE_BLERD_IQMIS
#define CyBle_cy_m0s8_ble__IV_MASTER0 CYREG_BLE_BLELL_IV_MASTER0
#define CyBle_cy_m0s8_ble__IV_MASTER1 CYREG_BLE_BLELL_IV_MASTER1
#define CyBle_cy_m0s8_ble__IV_SLAVE0 CYREG_BLE_BLELL_IV_SLAVE0
#define CyBle_cy_m0s8_ble__IV_SLAVE1 CYREG_BLE_BLELL_IV_SLAVE1
#define CyBle_cy_m0s8_ble__KVCAL CYREG_BLE_BLERD_KVCAL
#define CyBle_cy_m0s8_ble__LDO CYREG_BLE_BLERD_LDO
#define CyBle_cy_m0s8_ble__LDO_BYPASS CYREG_BLE_BLERD_LDO_BYPASS
#define CyBle_cy_m0s8_ble__LE_PING_TIMER_ADDR CYREG_BLE_BLELL_LE_PING_TIMER_ADDR
#define CyBle_cy_m0s8_ble__LE_PING_TIMER_NEXT_EXP CYREG_BLE_BLELL_LE_PING_TIMER_NEXT_EXP
#define CyBle_cy_m0s8_ble__LE_PING_TIMER_OFFSET CYREG_BLE_BLELL_LE_PING_TIMER_OFFSET
#define CyBle_cy_m0s8_ble__LE_PING_TIMER_WRAP_COUNT CYREG_BLE_BLELL_LE_PING_TIMER_WRAP_COUNT
#define CyBle_cy_m0s8_ble__LE_RF_TEST_MODE CYREG_BLE_BLELL_LE_RF_TEST_MODE
#define CyBle_cy_m0s8_ble__LF_CLK_CTRL CYREG_BLE_BLESS_LF_CLK_CTRL
#define CyBle_cy_m0s8_ble__LL_CLK_EN CYREG_BLE_BLESS_LL_CLK_EN
#define CyBle_cy_m0s8_ble__LL_DSM_CTRL CYREG_BLE_BLESS_LL_DSM_CTRL
#define CyBle_cy_m0s8_ble__LL_DSM_INTR_STAT CYREG_BLE_BLESS_LL_DSM_INTR_STAT
#define CyBle_cy_m0s8_ble__LLH_FEATURE_CONFIG CYREG_BLE_BLELL_LLH_FEATURE_CONFIG
#define CyBle_cy_m0s8_ble__MIC_IN0 CYREG_BLE_BLELL_MIC_IN0
#define CyBle_cy_m0s8_ble__MIC_IN1 CYREG_BLE_BLELL_MIC_IN1
#define CyBle_cy_m0s8_ble__MIC_OUT0 CYREG_BLE_BLELL_MIC_OUT0
#define CyBle_cy_m0s8_ble__MIC_OUT1 CYREG_BLE_BLELL_MIC_OUT1
#define CyBle_cy_m0s8_ble__MODEM CYREG_BLE_BLERD_MODEM
#define CyBle_cy_m0s8_ble__MONI CYREG_BLE_BLERD_MONI
#define CyBle_cy_m0s8_ble__NEXT_CE_INSTANT CYREG_BLE_BLELL_NEXT_CE_INSTANT
#define CyBle_cy_m0s8_ble__NEXT_RESP_TIMER_EXP CYREG_BLE_BLELL_NEXT_RESP_TIMER_EXP
#define CyBle_cy_m0s8_ble__NEXT_SUP_TO CYREG_BLE_BLELL_NEXT_SUP_TO
#define CyBle_cy_m0s8_ble__OFFSET_TO_FIRST_INSTANT CYREG_BLE_BLELL_OFFSET_TO_FIRST_INSTANT
#define CyBle_cy_m0s8_ble__PACKET_COUNTER0 CYREG_BLE_BLELL_PACKET_COUNTER0
#define CyBle_cy_m0s8_ble__PACKET_COUNTER1 CYREG_BLE_BLELL_PACKET_COUNTER1
#define CyBle_cy_m0s8_ble__PACKET_COUNTER2 CYREG_BLE_BLELL_PACKET_COUNTER2
#define CyBle_cy_m0s8_ble__PDU_ACCESS_ADDR_H_REGISTER CYREG_BLE_BLELL_PDU_ACCESS_ADDR_H_REGISTER
#define CyBle_cy_m0s8_ble__PDU_ACCESS_ADDR_L_REGISTER CYREG_BLE_BLELL_PDU_ACCESS_ADDR_L_REGISTER
#define CyBle_cy_m0s8_ble__PDU_RESP_TIMER CYREG_BLE_BLELL_PDU_RESP_TIMER
#define CyBle_cy_m0s8_ble__PEER_ADDR_H CYREG_BLE_BLELL_PEER_ADDR_H
#define CyBle_cy_m0s8_ble__PEER_ADDR_L CYREG_BLE_BLELL_PEER_ADDR_L
#define CyBle_cy_m0s8_ble__PEER_ADDR_M CYREG_BLE_BLELL_PEER_ADDR_M
#define CyBle_cy_m0s8_ble__POC_REG__TIM_CONTROL CYREG_BLE_BLELL_POC_REG__TIM_CONTROL
#define CyBle_cy_m0s8_ble__RCCAL CYREG_BLE_BLERD_RCCAL
#define CyBle_cy_m0s8_ble__READ_IQ_1 CYREG_BLE_BLERD_READ_IQ_1
#define CyBle_cy_m0s8_ble__READ_IQ_2 CYREG_BLE_BLERD_READ_IQ_2
#define CyBle_cy_m0s8_ble__READ_IQ_3 CYREG_BLE_BLERD_READ_IQ_3
#define CyBle_cy_m0s8_ble__READ_IQ_4 CYREG_BLE_BLERD_READ_IQ_4
#define CyBle_cy_m0s8_ble__RECEIVE_TRIG_CTRL CYREG_BLE_BLELL_RECEIVE_TRIG_CTRL
#define CyBle_cy_m0s8_ble__RF_CONFIG CYREG_BLE_BLESS_RF_CONFIG
#define CyBle_cy_m0s8_ble__RMAP CYREG_BLE_BLERD_RMAP
#define CyBle_cy_m0s8_ble__RSSI CYREG_BLE_BLERD_RSSI
#define CyBle_cy_m0s8_ble__RX CYREG_BLE_BLERD_RX
#define CyBle_cy_m0s8_ble__RX_BUMP1 CYREG_BLE_BLERD_RX_BUMP1
#define CyBle_cy_m0s8_ble__RX_BUMP2 CYREG_BLE_BLERD_RX_BUMP2
#define CyBle_cy_m0s8_ble__SCAN_CONFIG CYREG_BLE_BLELL_SCAN_CONFIG
#define CyBle_cy_m0s8_ble__SCAN_INTERVAL CYREG_BLE_BLELL_SCAN_INTERVAL
#define CyBle_cy_m0s8_ble__SCAN_INTR CYREG_BLE_BLELL_SCAN_INTR
#define CyBle_cy_m0s8_ble__SCAN_NEXT_INSTANT CYREG_BLE_BLELL_SCAN_NEXT_INSTANT
#define CyBle_cy_m0s8_ble__SCAN_PARAM CYREG_BLE_BLELL_SCAN_PARAM
#define CyBle_cy_m0s8_ble__SCAN_WINDOW CYREG_BLE_BLELL_SCAN_WINDOW
#define CyBle_cy_m0s8_ble__SL_CONN_INTERVAL CYREG_BLE_BLELL_SL_CONN_INTERVAL
#define CyBle_cy_m0s8_ble__SLAVE_LATENCY CYREG_BLE_BLELL_SLAVE_LATENCY
#define CyBle_cy_m0s8_ble__SLAVE_TIMING_CONTROL CYREG_BLE_BLELL_SLAVE_TIMING_CONTROL
#define CyBle_cy_m0s8_ble__SLV_WIN_ADJ CYREG_BLE_BLELL_SLV_WIN_ADJ
#define CyBle_cy_m0s8_ble__SUP_TIMEOUT CYREG_BLE_BLELL_SUP_TIMEOUT
#define CyBle_cy_m0s8_ble__SY CYREG_BLE_BLERD_SY
#define CyBle_cy_m0s8_ble__SY_BUMP1 CYREG_BLE_BLERD_SY_BUMP1
#define CyBle_cy_m0s8_ble__SY_BUMP2 CYREG_BLE_BLERD_SY_BUMP2
#define CyBle_cy_m0s8_ble__TEST CYREG_BLE_BLERD_TEST
#define CyBle_cy_m0s8_ble__TEST2_SY CYREG_BLE_BLERD_TEST2_SY
#define CyBle_cy_m0s8_ble__THRSHD1 CYREG_BLE_BLERD_THRSHD1
#define CyBle_cy_m0s8_ble__THRSHD2 CYREG_BLE_BLERD_THRSHD2
#define CyBle_cy_m0s8_ble__THRSHD3 CYREG_BLE_BLERD_THRSHD3
#define CyBle_cy_m0s8_ble__THRSHD4 CYREG_BLE_BLERD_THRSHD4
#define CyBle_cy_m0s8_ble__THRSHD5 CYREG_BLE_BLERD_THRSHD5
#define CyBle_cy_m0s8_ble__TIM_COUNTER_L CYREG_BLE_BLELL_TIM_COUNTER_L
#define CyBle_cy_m0s8_ble__TRANSMIT_WINDOW_OFFSET CYREG_BLE_BLELL_TRANSMIT_WINDOW_OFFSET
#define CyBle_cy_m0s8_ble__TRANSMIT_WINDOW_SIZE CYREG_BLE_BLELL_TRANSMIT_WINDOW_SIZE
#define CyBle_cy_m0s8_ble__TX CYREG_BLE_BLERD_TX
#define CyBle_cy_m0s8_ble__TX_BUMP1 CYREG_BLE_BLERD_TX_BUMP1
#define CyBle_cy_m0s8_ble__TX_BUMP2 CYREG_BLE_BLERD_TX_BUMP2
#define CyBle_cy_m0s8_ble__TX_EN_EXT_DELAY CYREG_BLE_BLELL_TX_EN_EXT_DELAY
#define CyBle_cy_m0s8_ble__TX_RX_ON_DELAY CYREG_BLE_BLELL_TX_RX_ON_DELAY
#define CyBle_cy_m0s8_ble__TX_RX_SYNTH_DELAY CYREG_BLE_BLELL_TX_RX_SYNTH_DELAY
#define CyBle_cy_m0s8_ble__TXRX_HOP CYREG_BLE_BLELL_TXRX_HOP
#define CyBle_cy_m0s8_ble__WAKEUP_CONFIG CYREG_BLE_BLELL_WAKEUP_CONFIG
#define CyBle_cy_m0s8_ble__WAKEUP_CONTROL CYREG_BLE_BLELL_WAKEUP_CONTROL
#define CyBle_cy_m0s8_ble__WCO_CONFIG CYREG_BLE_BLESS_WCO_CONFIG
#define CyBle_cy_m0s8_ble__WCO_STATUS CYREG_BLE_BLESS_WCO_STATUS
#define CyBle_cy_m0s8_ble__WCO_TRIM CYREG_BLE_BLESS_WCO_TRIM
#define CyBle_cy_m0s8_ble__WHITELIST_BASE_ADDR CYREG_BLE_BLELL_WHITELIST_BASE_ADDR
#define CyBle_cy_m0s8_ble__WIN_MIN_STEP_SIZE CYREG_BLE_BLELL_WIN_MIN_STEP_SIZE
#define CyBle_cy_m0s8_ble__WINDOW_WIDEN_INTVL CYREG_BLE_BLELL_WINDOW_WIDEN_INTVL
#define CyBle_cy_m0s8_ble__WINDOW_WIDEN_WINOFF CYREG_BLE_BLELL_WINDOW_WIDEN_WINOFF
#define CyBle_cy_m0s8_ble__WL_ADDR_TYPE CYREG_BLE_BLELL_WL_ADDR_TYPE
#define CyBle_cy_m0s8_ble__WL_ENABLE CYREG_BLE_BLELL_WL_ENABLE
#define CyBle_cy_m0s8_ble__XTAL_CLK_DIV_CONFIG CYREG_BLE_BLESS_XTAL_CLK_DIV_CONFIG

/* MIC_IN */
#define MIC_IN__0__DR CYREG_GPIO_PRT2_DR
#define MIC_IN__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define MIC_IN__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define MIC_IN__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define MIC_IN__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define MIC_IN__0__HSIOM_MASK 0x0000000Fu
#define MIC_IN__0__HSIOM_SHIFT 0u
#define MIC_IN__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define MIC_IN__0__INTR CYREG_GPIO_PRT2_INTR
#define MIC_IN__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define MIC_IN__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define MIC_IN__0__MASK 0x01u
#define MIC_IN__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define MIC_IN__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define MIC_IN__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define MIC_IN__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define MIC_IN__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define MIC_IN__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define MIC_IN__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define MIC_IN__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define MIC_IN__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define MIC_IN__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define MIC_IN__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define MIC_IN__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define MIC_IN__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define MIC_IN__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define MIC_IN__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define MIC_IN__0__PC CYREG_GPIO_PRT2_PC
#define MIC_IN__0__PC2 CYREG_GPIO_PRT2_PC2
#define MIC_IN__0__PORT 2u
#define MIC_IN__0__PS CYREG_GPIO_PRT2_PS
#define MIC_IN__0__SHIFT 0
#define MIC_IN__DR CYREG_GPIO_PRT2_DR
#define MIC_IN__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define MIC_IN__DR_INV CYREG_GPIO_PRT2_DR_INV
#define MIC_IN__DR_SET CYREG_GPIO_PRT2_DR_SET
#define MIC_IN__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define MIC_IN__INTR CYREG_GPIO_PRT2_INTR
#define MIC_IN__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define MIC_IN__INTSTAT CYREG_GPIO_PRT2_INTR
#define MIC_IN__MASK 0x01u
#define MIC_IN__PA__CFG0 CYREG_UDB_PA2_CFG0
#define MIC_IN__PA__CFG1 CYREG_UDB_PA2_CFG1
#define MIC_IN__PA__CFG10 CYREG_UDB_PA2_CFG10
#define MIC_IN__PA__CFG11 CYREG_UDB_PA2_CFG11
#define MIC_IN__PA__CFG12 CYREG_UDB_PA2_CFG12
#define MIC_IN__PA__CFG13 CYREG_UDB_PA2_CFG13
#define MIC_IN__PA__CFG14 CYREG_UDB_PA2_CFG14
#define MIC_IN__PA__CFG2 CYREG_UDB_PA2_CFG2
#define MIC_IN__PA__CFG3 CYREG_UDB_PA2_CFG3
#define MIC_IN__PA__CFG4 CYREG_UDB_PA2_CFG4
#define MIC_IN__PA__CFG5 CYREG_UDB_PA2_CFG5
#define MIC_IN__PA__CFG6 CYREG_UDB_PA2_CFG6
#define MIC_IN__PA__CFG7 CYREG_UDB_PA2_CFG7
#define MIC_IN__PA__CFG8 CYREG_UDB_PA2_CFG8
#define MIC_IN__PA__CFG9 CYREG_UDB_PA2_CFG9
#define MIC_IN__PC CYREG_GPIO_PRT2_PC
#define MIC_IN__PC2 CYREG_GPIO_PRT2_PC2
#define MIC_IN__PORT 2u
#define MIC_IN__PS CYREG_GPIO_PRT2_PS
#define MIC_IN__SHIFT 0

/* ADC_Pin */
#define ADC_Pin__0__DR CYREG_GPIO_PRT2_DR
#define ADC_Pin__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define ADC_Pin__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define ADC_Pin__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define ADC_Pin__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define ADC_Pin__0__HSIOM_MASK 0x000000F0u
#define ADC_Pin__0__HSIOM_SHIFT 4u
#define ADC_Pin__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define ADC_Pin__0__INTR CYREG_GPIO_PRT2_INTR
#define ADC_Pin__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define ADC_Pin__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define ADC_Pin__0__MASK 0x02u
#define ADC_Pin__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define ADC_Pin__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define ADC_Pin__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define ADC_Pin__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define ADC_Pin__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define ADC_Pin__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define ADC_Pin__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define ADC_Pin__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define ADC_Pin__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define ADC_Pin__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define ADC_Pin__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define ADC_Pin__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define ADC_Pin__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define ADC_Pin__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define ADC_Pin__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define ADC_Pin__0__PC CYREG_GPIO_PRT2_PC
#define ADC_Pin__0__PC2 CYREG_GPIO_PRT2_PC2
#define ADC_Pin__0__PORT 2u
#define ADC_Pin__0__PS CYREG_GPIO_PRT2_PS
#define ADC_Pin__0__SHIFT 1
#define ADC_Pin__DR CYREG_GPIO_PRT2_DR
#define ADC_Pin__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define ADC_Pin__DR_INV CYREG_GPIO_PRT2_DR_INV
#define ADC_Pin__DR_SET CYREG_GPIO_PRT2_DR_SET
#define ADC_Pin__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define ADC_Pin__INTR CYREG_GPIO_PRT2_INTR
#define ADC_Pin__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define ADC_Pin__INTSTAT CYREG_GPIO_PRT2_INTR
#define ADC_Pin__MASK 0x02u
#define ADC_Pin__PA__CFG0 CYREG_UDB_PA2_CFG0
#define ADC_Pin__PA__CFG1 CYREG_UDB_PA2_CFG1
#define ADC_Pin__PA__CFG10 CYREG_UDB_PA2_CFG10
#define ADC_Pin__PA__CFG11 CYREG_UDB_PA2_CFG11
#define ADC_Pin__PA__CFG12 CYREG_UDB_PA2_CFG12
#define ADC_Pin__PA__CFG13 CYREG_UDB_PA2_CFG13
#define ADC_Pin__PA__CFG14 CYREG_UDB_PA2_CFG14
#define ADC_Pin__PA__CFG2 CYREG_UDB_PA2_CFG2
#define ADC_Pin__PA__CFG3 CYREG_UDB_PA2_CFG3
#define ADC_Pin__PA__CFG4 CYREG_UDB_PA2_CFG4
#define ADC_Pin__PA__CFG5 CYREG_UDB_PA2_CFG5
#define ADC_Pin__PA__CFG6 CYREG_UDB_PA2_CFG6
#define ADC_Pin__PA__CFG7 CYREG_UDB_PA2_CFG7
#define ADC_Pin__PA__CFG8 CYREG_UDB_PA2_CFG8
#define ADC_Pin__PA__CFG9 CYREG_UDB_PA2_CFG9
#define ADC_Pin__PC CYREG_GPIO_PRT2_PC
#define ADC_Pin__PC2 CYREG_GPIO_PRT2_PC2
#define ADC_Pin__PORT 2u
#define ADC_Pin__PS CYREG_GPIO_PRT2_PS
#define ADC_Pin__SHIFT 1

/* Led_Pin */
#define Led_Pin__0__DR CYREG_GPIO_PRT5_DR
#define Led_Pin__0__DR_CLR CYREG_GPIO_PRT5_DR_CLR
#define Led_Pin__0__DR_INV CYREG_GPIO_PRT5_DR_INV
#define Led_Pin__0__DR_SET CYREG_GPIO_PRT5_DR_SET
#define Led_Pin__0__HSIOM CYREG_HSIOM_PORT_SEL5
#define Led_Pin__0__HSIOM_MASK 0x0000000Fu
#define Led_Pin__0__HSIOM_SHIFT 0u
#define Led_Pin__0__INTCFG CYREG_GPIO_PRT5_INTR_CFG
#define Led_Pin__0__INTR CYREG_GPIO_PRT5_INTR
#define Led_Pin__0__INTR_CFG CYREG_GPIO_PRT5_INTR_CFG
#define Led_Pin__0__INTSTAT CYREG_GPIO_PRT5_INTR
#define Led_Pin__0__MASK 0x01u
#define Led_Pin__0__PC CYREG_GPIO_PRT5_PC
#define Led_Pin__0__PC2 CYREG_GPIO_PRT5_PC2
#define Led_Pin__0__PORT 5u
#define Led_Pin__0__PS CYREG_GPIO_PRT5_PS
#define Led_Pin__0__SHIFT 0
#define Led_Pin__DR CYREG_GPIO_PRT5_DR
#define Led_Pin__DR_CLR CYREG_GPIO_PRT5_DR_CLR
#define Led_Pin__DR_INV CYREG_GPIO_PRT5_DR_INV
#define Led_Pin__DR_SET CYREG_GPIO_PRT5_DR_SET
#define Led_Pin__INTCFG CYREG_GPIO_PRT5_INTR_CFG
#define Led_Pin__INTR CYREG_GPIO_PRT5_INTR
#define Led_Pin__INTR_CFG CYREG_GPIO_PRT5_INTR_CFG
#define Led_Pin__INTSTAT CYREG_GPIO_PRT5_INTR
#define Led_Pin__MASK 0x01u
#define Led_Pin__PC CYREG_GPIO_PRT5_PC
#define Led_Pin__PC2 CYREG_GPIO_PRT5_PC2
#define Led_Pin__PORT 5u
#define Led_Pin__PS CYREG_GPIO_PRT5_PS
#define Led_Pin__SHIFT 0

/* Opamp_1_cy_psoc4_abuf */
#define Opamp_1_cy_psoc4_abuf__COMP_STAT CYREG_CTBM0_COMP_STAT
#define Opamp_1_cy_psoc4_abuf__COMP_STAT_SHIFT 16
#define Opamp_1_cy_psoc4_abuf__CTBM_CTB_CTRL CYREG_CTBM0_CTB_CTRL
#define Opamp_1_cy_psoc4_abuf__INTR CYREG_CTBM0_INTR
#define Opamp_1_cy_psoc4_abuf__INTR_MASK CYREG_CTBM0_INTR_MASK
#define Opamp_1_cy_psoc4_abuf__INTR_MASK_SHIFT 1
#define Opamp_1_cy_psoc4_abuf__INTR_MASKED CYREG_CTBM0_INTR_MASKED
#define Opamp_1_cy_psoc4_abuf__INTR_MASKED_SHIFT 1
#define Opamp_1_cy_psoc4_abuf__INTR_SET CYREG_CTBM0_INTR_SET
#define Opamp_1_cy_psoc4_abuf__INTR_SET_SHIFT 1
#define Opamp_1_cy_psoc4_abuf__INTR_SHIFT 1
#define Opamp_1_cy_psoc4_abuf__OA_COMP_TRIM CYREG_CTBM0_OA1_COMP_TRIM
#define Opamp_1_cy_psoc4_abuf__OA_NUMBER 1u
#define Opamp_1_cy_psoc4_abuf__OA_OFFSET_TRIM CYREG_CTBM0_OA1_OFFSET_TRIM
#define Opamp_1_cy_psoc4_abuf__OA_RES_CTRL CYREG_CTBM0_OA_RES1_CTRL
#define Opamp_1_cy_psoc4_abuf__OA_SLOPE_OFFSET_TRIM CYREG_CTBM0_OA1_SLOPE_OFFSET_TRIM

/* Opamp_2_cy_psoc4_abuf */
#define Opamp_2_cy_psoc4_abuf__COMP_STAT CYREG_CTBM0_COMP_STAT
#define Opamp_2_cy_psoc4_abuf__COMP_STAT_SHIFT 0
#define Opamp_2_cy_psoc4_abuf__CTBM_CTB_CTRL CYREG_CTBM0_CTB_CTRL
#define Opamp_2_cy_psoc4_abuf__INTR CYREG_CTBM0_INTR
#define Opamp_2_cy_psoc4_abuf__INTR_MASK CYREG_CTBM0_INTR_MASK
#define Opamp_2_cy_psoc4_abuf__INTR_MASK_SHIFT 0
#define Opamp_2_cy_psoc4_abuf__INTR_MASKED CYREG_CTBM0_INTR_MASKED
#define Opamp_2_cy_psoc4_abuf__INTR_MASKED_SHIFT 0
#define Opamp_2_cy_psoc4_abuf__INTR_SET CYREG_CTBM0_INTR_SET
#define Opamp_2_cy_psoc4_abuf__INTR_SET_SHIFT 0
#define Opamp_2_cy_psoc4_abuf__INTR_SHIFT 0
#define Opamp_2_cy_psoc4_abuf__OA_COMP_TRIM CYREG_CTBM0_OA0_COMP_TRIM
#define Opamp_2_cy_psoc4_abuf__OA_NUMBER 0u
#define Opamp_2_cy_psoc4_abuf__OA_OFFSET_TRIM CYREG_CTBM0_OA0_OFFSET_TRIM
#define Opamp_2_cy_psoc4_abuf__OA_RES_CTRL CYREG_CTBM0_OA_RES0_CTRL
#define Opamp_2_cy_psoc4_abuf__OA_SLOPE_OFFSET_TRIM CYREG_CTBM0_OA0_SLOPE_OFFSET_TRIM

/* Timer_1_cy_m0s8_tcpwm_1 */
#define Timer_1_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT0_CC
#define Timer_1_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT0_CC_BUFF
#define Timer_1_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT0_COUNTER
#define Timer_1_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT0_CTRL
#define Timer_1_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT0_INTR
#define Timer_1_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT0_INTR_MASK
#define Timer_1_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT0_INTR_MASKED
#define Timer_1_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT0_INTR_SET
#define Timer_1_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT0_PERIOD
#define Timer_1_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT0_PERIOD_BUFF
#define Timer_1_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT0_STATUS
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x01u
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 0
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x100u
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 8
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x1000000u
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 24
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x10000u
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 16
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x01u
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 0
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x01u
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 0
#define Timer_1_cy_m0s8_tcpwm_1__TCPWM_NUMBER 0u
#define Timer_1_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT0_TR_CTRL0
#define Timer_1_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT0_TR_CTRL1
#define Timer_1_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT0_TR_CTRL2

/* Audio_EN */
#define Audio_EN__0__DR CYREG_GPIO_PRT4_DR
#define Audio_EN__0__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define Audio_EN__0__DR_INV CYREG_GPIO_PRT4_DR_INV
#define Audio_EN__0__DR_SET CYREG_GPIO_PRT4_DR_SET
#define Audio_EN__0__HSIOM CYREG_HSIOM_PORT_SEL4
#define Audio_EN__0__HSIOM_MASK 0x000000F0u
#define Audio_EN__0__HSIOM_SHIFT 4u
#define Audio_EN__0__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define Audio_EN__0__INTR CYREG_GPIO_PRT4_INTR
#define Audio_EN__0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define Audio_EN__0__INTSTAT CYREG_GPIO_PRT4_INTR
#define Audio_EN__0__MASK 0x02u
#define Audio_EN__0__PC CYREG_GPIO_PRT4_PC
#define Audio_EN__0__PC2 CYREG_GPIO_PRT4_PC2
#define Audio_EN__0__PORT 4u
#define Audio_EN__0__PS CYREG_GPIO_PRT4_PS
#define Audio_EN__0__SHIFT 1
#define Audio_EN__DR CYREG_GPIO_PRT4_DR
#define Audio_EN__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define Audio_EN__DR_INV CYREG_GPIO_PRT4_DR_INV
#define Audio_EN__DR_SET CYREG_GPIO_PRT4_DR_SET
#define Audio_EN__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define Audio_EN__INTR CYREG_GPIO_PRT4_INTR
#define Audio_EN__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define Audio_EN__INTSTAT CYREG_GPIO_PRT4_INTR
#define Audio_EN__MASK 0x02u
#define Audio_EN__PC CYREG_GPIO_PRT4_PC
#define Audio_EN__PC2 CYREG_GPIO_PRT4_PC2
#define Audio_EN__PORT 4u
#define Audio_EN__PS CYREG_GPIO_PRT4_PS
#define Audio_EN__SHIFT 1

/* Audio_Pin */
#define Audio_Pin__0__DR CYREG_GPIO_PRT2_DR
#define Audio_Pin__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Audio_Pin__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Audio_Pin__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Audio_Pin__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define Audio_Pin__0__HSIOM_MASK 0x00F00000u
#define Audio_Pin__0__HSIOM_SHIFT 20u
#define Audio_Pin__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Audio_Pin__0__INTR CYREG_GPIO_PRT2_INTR
#define Audio_Pin__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Audio_Pin__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define Audio_Pin__0__MASK 0x20u
#define Audio_Pin__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Audio_Pin__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Audio_Pin__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Audio_Pin__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Audio_Pin__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Audio_Pin__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Audio_Pin__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Audio_Pin__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Audio_Pin__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Audio_Pin__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Audio_Pin__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Audio_Pin__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Audio_Pin__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Audio_Pin__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Audio_Pin__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Audio_Pin__0__PC CYREG_GPIO_PRT2_PC
#define Audio_Pin__0__PC2 CYREG_GPIO_PRT2_PC2
#define Audio_Pin__0__PORT 2u
#define Audio_Pin__0__PS CYREG_GPIO_PRT2_PS
#define Audio_Pin__0__SHIFT 5
#define Audio_Pin__DR CYREG_GPIO_PRT2_DR
#define Audio_Pin__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define Audio_Pin__DR_INV CYREG_GPIO_PRT2_DR_INV
#define Audio_Pin__DR_SET CYREG_GPIO_PRT2_DR_SET
#define Audio_Pin__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define Audio_Pin__INTR CYREG_GPIO_PRT2_INTR
#define Audio_Pin__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define Audio_Pin__INTSTAT CYREG_GPIO_PRT2_INTR
#define Audio_Pin__MASK 0x20u
#define Audio_Pin__PA__CFG0 CYREG_UDB_PA2_CFG0
#define Audio_Pin__PA__CFG1 CYREG_UDB_PA2_CFG1
#define Audio_Pin__PA__CFG10 CYREG_UDB_PA2_CFG10
#define Audio_Pin__PA__CFG11 CYREG_UDB_PA2_CFG11
#define Audio_Pin__PA__CFG12 CYREG_UDB_PA2_CFG12
#define Audio_Pin__PA__CFG13 CYREG_UDB_PA2_CFG13
#define Audio_Pin__PA__CFG14 CYREG_UDB_PA2_CFG14
#define Audio_Pin__PA__CFG2 CYREG_UDB_PA2_CFG2
#define Audio_Pin__PA__CFG3 CYREG_UDB_PA2_CFG3
#define Audio_Pin__PA__CFG4 CYREG_UDB_PA2_CFG4
#define Audio_Pin__PA__CFG5 CYREG_UDB_PA2_CFG5
#define Audio_Pin__PA__CFG6 CYREG_UDB_PA2_CFG6
#define Audio_Pin__PA__CFG7 CYREG_UDB_PA2_CFG7
#define Audio_Pin__PA__CFG8 CYREG_UDB_PA2_CFG8
#define Audio_Pin__PA__CFG9 CYREG_UDB_PA2_CFG9
#define Audio_Pin__PC CYREG_GPIO_PRT2_PC
#define Audio_Pin__PC2 CYREG_GPIO_PRT2_PC2
#define Audio_Pin__PORT 2u
#define Audio_Pin__PS CYREG_GPIO_PRT2_PS
#define Audio_Pin__SHIFT 5

/* Prism_Led_Clock */
#define Prism_Led_Clock__CTRL_REGISTER CYREG_PERI_PCLK_CTL10
#define Prism_Led_Clock__DIV_ID 0x00000043u
#define Prism_Led_Clock__DIV_REGISTER CYREG_PERI_DIV_16_CTL3
#define Prism_Led_Clock__PA_DIV_ID 0x000000FFu

/* Prism_Led_cy_m0s8_tcpwm_1 */
#define Prism_Led_cy_m0s8_tcpwm_1__CC CYREG_TCPWM_CNT3_CC
#define Prism_Led_cy_m0s8_tcpwm_1__CC_BUFF CYREG_TCPWM_CNT3_CC_BUFF
#define Prism_Led_cy_m0s8_tcpwm_1__COUNTER CYREG_TCPWM_CNT3_COUNTER
#define Prism_Led_cy_m0s8_tcpwm_1__CTRL CYREG_TCPWM_CNT3_CTRL
#define Prism_Led_cy_m0s8_tcpwm_1__INTR CYREG_TCPWM_CNT3_INTR
#define Prism_Led_cy_m0s8_tcpwm_1__INTR_MASK CYREG_TCPWM_CNT3_INTR_MASK
#define Prism_Led_cy_m0s8_tcpwm_1__INTR_MASKED CYREG_TCPWM_CNT3_INTR_MASKED
#define Prism_Led_cy_m0s8_tcpwm_1__INTR_SET CYREG_TCPWM_CNT3_INTR_SET
#define Prism_Led_cy_m0s8_tcpwm_1__PERIOD CYREG_TCPWM_CNT3_PERIOD
#define Prism_Led_cy_m0s8_tcpwm_1__PERIOD_BUFF CYREG_TCPWM_CNT3_PERIOD_BUFF
#define Prism_Led_cy_m0s8_tcpwm_1__STATUS CYREG_TCPWM_CNT3_STATUS
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMD CYREG_TCPWM_CMD
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_MASK 0x08u
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMDCAPTURE_SHIFT 3
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_MASK 0x800u
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMDRELOAD_SHIFT 11
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_MASK 0x8000000u
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMDSTART_SHIFT 27
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_MASK 0x80000u
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CMDSTOP_SHIFT 19
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CTRL CYREG_TCPWM_CTRL
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CTRL_MASK 0x08u
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_CTRL_SHIFT 3
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE CYREG_TCPWM_INTR_CAUSE
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_MASK 0x08u
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_INTR_CAUSE_SHIFT 3
#define Prism_Led_cy_m0s8_tcpwm_1__TCPWM_NUMBER 3u
#define Prism_Led_cy_m0s8_tcpwm_1__TR_CTRL0 CYREG_TCPWM_CNT3_TR_CTRL0
#define Prism_Led_cy_m0s8_tcpwm_1__TR_CTRL1 CYREG_TCPWM_CNT3_TR_CTRL1
#define Prism_Led_cy_m0s8_tcpwm_1__TR_CTRL2 CYREG_TCPWM_CNT3_TR_CTRL2

/* FILTER_OUT */
#define FILTER_OUT__0__DR CYREG_GPIO_PRT2_DR
#define FILTER_OUT__0__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define FILTER_OUT__0__DR_INV CYREG_GPIO_PRT2_DR_INV
#define FILTER_OUT__0__DR_SET CYREG_GPIO_PRT2_DR_SET
#define FILTER_OUT__0__HSIOM CYREG_HSIOM_PORT_SEL2
#define FILTER_OUT__0__HSIOM_MASK 0x00000F00u
#define FILTER_OUT__0__HSIOM_SHIFT 8u
#define FILTER_OUT__0__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define FILTER_OUT__0__INTR CYREG_GPIO_PRT2_INTR
#define FILTER_OUT__0__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define FILTER_OUT__0__INTSTAT CYREG_GPIO_PRT2_INTR
#define FILTER_OUT__0__MASK 0x04u
#define FILTER_OUT__0__PA__CFG0 CYREG_UDB_PA2_CFG0
#define FILTER_OUT__0__PA__CFG1 CYREG_UDB_PA2_CFG1
#define FILTER_OUT__0__PA__CFG10 CYREG_UDB_PA2_CFG10
#define FILTER_OUT__0__PA__CFG11 CYREG_UDB_PA2_CFG11
#define FILTER_OUT__0__PA__CFG12 CYREG_UDB_PA2_CFG12
#define FILTER_OUT__0__PA__CFG13 CYREG_UDB_PA2_CFG13
#define FILTER_OUT__0__PA__CFG14 CYREG_UDB_PA2_CFG14
#define FILTER_OUT__0__PA__CFG2 CYREG_UDB_PA2_CFG2
#define FILTER_OUT__0__PA__CFG3 CYREG_UDB_PA2_CFG3
#define FILTER_OUT__0__PA__CFG4 CYREG_UDB_PA2_CFG4
#define FILTER_OUT__0__PA__CFG5 CYREG_UDB_PA2_CFG5
#define FILTER_OUT__0__PA__CFG6 CYREG_UDB_PA2_CFG6
#define FILTER_OUT__0__PA__CFG7 CYREG_UDB_PA2_CFG7
#define FILTER_OUT__0__PA__CFG8 CYREG_UDB_PA2_CFG8
#define FILTER_OUT__0__PA__CFG9 CYREG_UDB_PA2_CFG9
#define FILTER_OUT__0__PC CYREG_GPIO_PRT2_PC
#define FILTER_OUT__0__PC2 CYREG_GPIO_PRT2_PC2
#define FILTER_OUT__0__PORT 2u
#define FILTER_OUT__0__PS CYREG_GPIO_PRT2_PS
#define FILTER_OUT__0__SHIFT 2
#define FILTER_OUT__DR CYREG_GPIO_PRT2_DR
#define FILTER_OUT__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define FILTER_OUT__DR_INV CYREG_GPIO_PRT2_DR_INV
#define FILTER_OUT__DR_SET CYREG_GPIO_PRT2_DR_SET
#define FILTER_OUT__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define FILTER_OUT__INTR CYREG_GPIO_PRT2_INTR
#define FILTER_OUT__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define FILTER_OUT__INTSTAT CYREG_GPIO_PRT2_INTR
#define FILTER_OUT__MASK 0x04u
#define FILTER_OUT__PA__CFG0 CYREG_UDB_PA2_CFG0
#define FILTER_OUT__PA__CFG1 CYREG_UDB_PA2_CFG1
#define FILTER_OUT__PA__CFG10 CYREG_UDB_PA2_CFG10
#define FILTER_OUT__PA__CFG11 CYREG_UDB_PA2_CFG11
#define FILTER_OUT__PA__CFG12 CYREG_UDB_PA2_CFG12
#define FILTER_OUT__PA__CFG13 CYREG_UDB_PA2_CFG13
#define FILTER_OUT__PA__CFG14 CYREG_UDB_PA2_CFG14
#define FILTER_OUT__PA__CFG2 CYREG_UDB_PA2_CFG2
#define FILTER_OUT__PA__CFG3 CYREG_UDB_PA2_CFG3
#define FILTER_OUT__PA__CFG4 CYREG_UDB_PA2_CFG4
#define FILTER_OUT__PA__CFG5 CYREG_UDB_PA2_CFG5
#define FILTER_OUT__PA__CFG6 CYREG_UDB_PA2_CFG6
#define FILTER_OUT__PA__CFG7 CYREG_UDB_PA2_CFG7
#define FILTER_OUT__PA__CFG8 CYREG_UDB_PA2_CFG8
#define FILTER_OUT__PA__CFG9 CYREG_UDB_PA2_CFG9
#define FILTER_OUT__PC CYREG_GPIO_PRT2_PC
#define FILTER_OUT__PC2 CYREG_GPIO_PRT2_PC2
#define FILTER_OUT__PORT 2u
#define FILTER_OUT__PS CYREG_GPIO_PRT2_PS
#define FILTER_OUT__SHIFT 2

/* SW_Tx_UART_tx */
#define SW_Tx_UART_tx__0__DR CYREG_GPIO_PRT0_DR
#define SW_Tx_UART_tx__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define SW_Tx_UART_tx__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define SW_Tx_UART_tx__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define SW_Tx_UART_tx__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define SW_Tx_UART_tx__0__HSIOM_MASK 0x00F00000u
#define SW_Tx_UART_tx__0__HSIOM_SHIFT 20u
#define SW_Tx_UART_tx__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define SW_Tx_UART_tx__0__INTR CYREG_GPIO_PRT0_INTR
#define SW_Tx_UART_tx__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define SW_Tx_UART_tx__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define SW_Tx_UART_tx__0__MASK 0x20u
#define SW_Tx_UART_tx__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define SW_Tx_UART_tx__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define SW_Tx_UART_tx__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define SW_Tx_UART_tx__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define SW_Tx_UART_tx__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define SW_Tx_UART_tx__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define SW_Tx_UART_tx__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define SW_Tx_UART_tx__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define SW_Tx_UART_tx__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define SW_Tx_UART_tx__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define SW_Tx_UART_tx__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define SW_Tx_UART_tx__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define SW_Tx_UART_tx__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define SW_Tx_UART_tx__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define SW_Tx_UART_tx__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define SW_Tx_UART_tx__0__PC CYREG_GPIO_PRT0_PC
#define SW_Tx_UART_tx__0__PC2 CYREG_GPIO_PRT0_PC2
#define SW_Tx_UART_tx__0__PORT 0u
#define SW_Tx_UART_tx__0__PS CYREG_GPIO_PRT0_PS
#define SW_Tx_UART_tx__0__SHIFT 5
#define SW_Tx_UART_tx__DR CYREG_GPIO_PRT0_DR
#define SW_Tx_UART_tx__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define SW_Tx_UART_tx__DR_INV CYREG_GPIO_PRT0_DR_INV
#define SW_Tx_UART_tx__DR_SET CYREG_GPIO_PRT0_DR_SET
#define SW_Tx_UART_tx__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define SW_Tx_UART_tx__INTR CYREG_GPIO_PRT0_INTR
#define SW_Tx_UART_tx__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define SW_Tx_UART_tx__INTSTAT CYREG_GPIO_PRT0_INTR
#define SW_Tx_UART_tx__MASK 0x20u
#define SW_Tx_UART_tx__PA__CFG0 CYREG_UDB_PA0_CFG0
#define SW_Tx_UART_tx__PA__CFG1 CYREG_UDB_PA0_CFG1
#define SW_Tx_UART_tx__PA__CFG10 CYREG_UDB_PA0_CFG10
#define SW_Tx_UART_tx__PA__CFG11 CYREG_UDB_PA0_CFG11
#define SW_Tx_UART_tx__PA__CFG12 CYREG_UDB_PA0_CFG12
#define SW_Tx_UART_tx__PA__CFG13 CYREG_UDB_PA0_CFG13
#define SW_Tx_UART_tx__PA__CFG14 CYREG_UDB_PA0_CFG14
#define SW_Tx_UART_tx__PA__CFG2 CYREG_UDB_PA0_CFG2
#define SW_Tx_UART_tx__PA__CFG3 CYREG_UDB_PA0_CFG3
#define SW_Tx_UART_tx__PA__CFG4 CYREG_UDB_PA0_CFG4
#define SW_Tx_UART_tx__PA__CFG5 CYREG_UDB_PA0_CFG5
#define SW_Tx_UART_tx__PA__CFG6 CYREG_UDB_PA0_CFG6
#define SW_Tx_UART_tx__PA__CFG7 CYREG_UDB_PA0_CFG7
#define SW_Tx_UART_tx__PA__CFG8 CYREG_UDB_PA0_CFG8
#define SW_Tx_UART_tx__PA__CFG9 CYREG_UDB_PA0_CFG9
#define SW_Tx_UART_tx__PC CYREG_GPIO_PRT0_PC
#define SW_Tx_UART_tx__PC2 CYREG_GPIO_PRT0_PC2
#define SW_Tx_UART_tx__PORT 0u
#define SW_Tx_UART_tx__PS CYREG_GPIO_PRT0_PS
#define SW_Tx_UART_tx__SHIFT 5

/* ADC_SAR_SEQ_cy_psoc4_sar */
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_CTRL CYREG_SAR_CTRL
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_INTR CYREG_SAR_INTR
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_INTR_CAUSE CYREG_SAR_INTR_CAUSE
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_INTR_MASK CYREG_SAR_INTR_MASK
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_INTR_MASKED CYREG_SAR_INTR_MASKED
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_INTR_SET CYREG_SAR_INTR_SET
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_NUMBER 0u
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_RANGE_COND CYREG_SAR_RANGE_COND
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_RANGE_INTR_MASK CYREG_SAR_RANGE_INTR_MASK
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_RANGE_INTR_MASKED CYREG_SAR_RANGE_INTR_MASKED
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_RANGE_INTR_SET CYREG_SAR_RANGE_INTR_SET
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_RANGE_THRES CYREG_SAR_RANGE_THRES
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_SAMPLE_CTRL CYREG_SAR_SAMPLE_CTRL
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_SAMPLE_TIME01 CYREG_SAR_SAMPLE_TIME01
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_SAMPLE_TIME23 CYREG_SAR_SAMPLE_TIME23
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_SATURATE_INTR_MASK CYREG_SAR_SATURATE_INTR_MASK
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_SATURATE_INTR_MASKED CYREG_SAR_SATURATE_INTR_MASKED
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_SATURATE_INTR_SET CYREG_SAR_SATURATE_INTR_SET
#define ADC_SAR_SEQ_cy_psoc4_sar__SAR_STATUS CYREG_SAR_STATUS

/* ADC_SAR_SEQ_intClock */
#define ADC_SAR_SEQ_intClock__CTRL_REGISTER CYREG_PERI_PCLK_CTL6
#define ADC_SAR_SEQ_intClock__DIV_ID 0x00000045u
#define ADC_SAR_SEQ_intClock__DIV_REGISTER CYREG_PERI_DIV_16_CTL5
#define ADC_SAR_SEQ_intClock__PA_DIV_ID 0x000000FFu

/* ADC_SAR_SEQ_IRQ */
#define ADC_SAR_SEQ_IRQ__INTC_CLR_EN_REG CYREG_CM0_ICER
#define ADC_SAR_SEQ_IRQ__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define ADC_SAR_SEQ_IRQ__INTC_MASK 0x8000u
#define ADC_SAR_SEQ_IRQ__INTC_NUMBER 15u
#define ADC_SAR_SEQ_IRQ__INTC_PRIOR_MASK 0xC0000000u
#define ADC_SAR_SEQ_IRQ__INTC_PRIOR_NUM 3u
#define ADC_SAR_SEQ_IRQ__INTC_PRIOR_REG CYREG_CM0_IPR3
#define ADC_SAR_SEQ_IRQ__INTC_SET_EN_REG CYREG_CM0_ISER
#define ADC_SAR_SEQ_IRQ__INTC_SET_PD_REG CYREG_CM0_ISPR

/* CSD_Touchpad_Cmod */
#define CSD_Touchpad_Cmod__0__DR CYREG_GPIO_PRT4_DR
#define CSD_Touchpad_Cmod__0__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CSD_Touchpad_Cmod__0__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CSD_Touchpad_Cmod__0__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CSD_Touchpad_Cmod__0__HSIOM CYREG_HSIOM_PORT_SEL4
#define CSD_Touchpad_Cmod__0__HSIOM_MASK 0x0000000Fu
#define CSD_Touchpad_Cmod__0__HSIOM_SHIFT 0u
#define CSD_Touchpad_Cmod__0__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CSD_Touchpad_Cmod__0__INTR CYREG_GPIO_PRT4_INTR
#define CSD_Touchpad_Cmod__0__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CSD_Touchpad_Cmod__0__INTSTAT CYREG_GPIO_PRT4_INTR
#define CSD_Touchpad_Cmod__0__MASK 0x01u
#define CSD_Touchpad_Cmod__0__PC CYREG_GPIO_PRT4_PC
#define CSD_Touchpad_Cmod__0__PC2 CYREG_GPIO_PRT4_PC2
#define CSD_Touchpad_Cmod__0__PORT 4u
#define CSD_Touchpad_Cmod__0__PS CYREG_GPIO_PRT4_PS
#define CSD_Touchpad_Cmod__0__SHIFT 0
#define CSD_Touchpad_Cmod__Cmod__DR CYREG_GPIO_PRT4_DR
#define CSD_Touchpad_Cmod__Cmod__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CSD_Touchpad_Cmod__Cmod__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CSD_Touchpad_Cmod__Cmod__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CSD_Touchpad_Cmod__Cmod__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CSD_Touchpad_Cmod__Cmod__INTR CYREG_GPIO_PRT4_INTR
#define CSD_Touchpad_Cmod__Cmod__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CSD_Touchpad_Cmod__Cmod__INTSTAT CYREG_GPIO_PRT4_INTR
#define CSD_Touchpad_Cmod__Cmod__MASK 0x01u
#define CSD_Touchpad_Cmod__Cmod__PC CYREG_GPIO_PRT4_PC
#define CSD_Touchpad_Cmod__Cmod__PC2 CYREG_GPIO_PRT4_PC2
#define CSD_Touchpad_Cmod__Cmod__PORT 4u
#define CSD_Touchpad_Cmod__Cmod__PS CYREG_GPIO_PRT4_PS
#define CSD_Touchpad_Cmod__Cmod__SHIFT 0
#define CSD_Touchpad_Cmod__DR CYREG_GPIO_PRT4_DR
#define CSD_Touchpad_Cmod__DR_CLR CYREG_GPIO_PRT4_DR_CLR
#define CSD_Touchpad_Cmod__DR_INV CYREG_GPIO_PRT4_DR_INV
#define CSD_Touchpad_Cmod__DR_SET CYREG_GPIO_PRT4_DR_SET
#define CSD_Touchpad_Cmod__INTCFG CYREG_GPIO_PRT4_INTR_CFG
#define CSD_Touchpad_Cmod__INTR CYREG_GPIO_PRT4_INTR
#define CSD_Touchpad_Cmod__INTR_CFG CYREG_GPIO_PRT4_INTR_CFG
#define CSD_Touchpad_Cmod__INTSTAT CYREG_GPIO_PRT4_INTR
#define CSD_Touchpad_Cmod__MASK 0x01u
#define CSD_Touchpad_Cmod__PC CYREG_GPIO_PRT4_PC
#define CSD_Touchpad_Cmod__PC2 CYREG_GPIO_PRT4_PC2
#define CSD_Touchpad_Cmod__PORT 4u
#define CSD_Touchpad_Cmod__PS CYREG_GPIO_PRT4_PS
#define CSD_Touchpad_Cmod__SHIFT 0

/* CSD_Touchpad_CSD_FFB */
#define CSD_Touchpad_CSD_FFB__CSD_CONFIG CYREG_CSD_CONFIG
#define CSD_Touchpad_CSD_FFB__CSD_COUNTER CYREG_CSD_COUNTER
#define CSD_Touchpad_CSD_FFB__CSD_ID CYREG_CSD_ID
#define CSD_Touchpad_CSD_FFB__CSD_INTR CYREG_CSD_INTR
#define CSD_Touchpad_CSD_FFB__CSD_INTR_SET CYREG_CSD_INTR_SET
#define CSD_Touchpad_CSD_FFB__CSD_NUMBER 0u
#define CSD_Touchpad_CSD_FFB__CSD_PWM CYREG_CSD_PWM
#define CSD_Touchpad_CSD_FFB__CSD_STATUS CYREG_CSD_STATUS

/* CSD_Touchpad_IDAC1_cy_psoc4_idac */
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__CONTROL CYREG_CSD_CONFIG
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__CSD_IDAC CYREG_CSD_IDAC
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__CSD_IDAC_SHIFT 0
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__CSD_TRIM1 CYREG_CSD_TRIM1
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__CSD_TRIM1_SHIFT 0
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__CSD_TRIM2 CYREG_CSD_TRIM2
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__CSD_TRIM2_SHIFT 0
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__IDAC_NUMBER 1u
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__POLARITY CYREG_CSD_CONFIG
#define CSD_Touchpad_IDAC1_cy_psoc4_idac__POLARITY_SHIFT 16

/* CSD_Touchpad_IDAC2_cy_psoc4_idac */
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__CONTROL CYREG_CSD_CONFIG
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__CSD_IDAC CYREG_CSD_IDAC
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__CSD_IDAC_SHIFT 16
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__CSD_TRIM1 CYREG_CSD_TRIM1
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__CSD_TRIM1_SHIFT 4
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__CSD_TRIM2 CYREG_CSD_TRIM2
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__CSD_TRIM2_SHIFT 4
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__IDAC_NUMBER 2u
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__POLARITY CYREG_CSD_CONFIG
#define CSD_Touchpad_IDAC2_cy_psoc4_idac__POLARITY_SHIFT 17

/* CSD_Touchpad_ISR */
#define CSD_Touchpad_ISR__INTC_CLR_EN_REG CYREG_CM0_ICER
#define CSD_Touchpad_ISR__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define CSD_Touchpad_ISR__INTC_MASK 0x10000u
#define CSD_Touchpad_ISR__INTC_NUMBER 16u
#define CSD_Touchpad_ISR__INTC_PRIOR_MASK 0xC0u
#define CSD_Touchpad_ISR__INTC_PRIOR_NUM 3u
#define CSD_Touchpad_ISR__INTC_PRIOR_REG CYREG_CM0_IPR4
#define CSD_Touchpad_ISR__INTC_SET_EN_REG CYREG_CM0_ISER
#define CSD_Touchpad_ISR__INTC_SET_PD_REG CYREG_CM0_ISPR

/* CSD_Touchpad_SampleClk */
#define CSD_Touchpad_SampleClk__CTRL_REGISTER CYREG_PERI_PCLK_CTL5
#define CSD_Touchpad_SampleClk__DIV_ID 0x00000040u
#define CSD_Touchpad_SampleClk__DIV_REGISTER CYREG_PERI_DIV_16_CTL0
#define CSD_Touchpad_SampleClk__PA_DIV_ID 0x000000FFu

/* CSD_Touchpad_SenseClk */
#define CSD_Touchpad_SenseClk__CTRL_REGISTER CYREG_PERI_PCLK_CTL4
#define CSD_Touchpad_SenseClk__DIV_ID 0x00000041u
#define CSD_Touchpad_SenseClk__DIV_REGISTER CYREG_PERI_DIV_16_CTL1
#define CSD_Touchpad_SenseClk__PA_DIV_ID 0x000000FFu

/* CSD_Touchpad_Sns */
#define CSD_Touchpad_Sns__0__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__0__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__0__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__0__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__0__HSIOM CYREG_HSIOM_PORT_SEL3
#define CSD_Touchpad_Sns__0__HSIOM_MASK 0x0000F000u
#define CSD_Touchpad_Sns__0__HSIOM_SHIFT 12u
#define CSD_Touchpad_Sns__0__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__0__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__0__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__0__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__0__MASK 0x08u
#define CSD_Touchpad_Sns__0__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__0__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__0__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__0__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__0__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__0__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__0__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__0__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__0__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__0__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__0__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__0__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__0__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__0__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__0__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__0__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__0__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__0__PORT 3u
#define CSD_Touchpad_Sns__0__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__0__SHIFT 3
#define CSD_Touchpad_Sns__1__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__1__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__1__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__1__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__1__HSIOM CYREG_HSIOM_PORT_SEL3
#define CSD_Touchpad_Sns__1__HSIOM_MASK 0x000F0000u
#define CSD_Touchpad_Sns__1__HSIOM_SHIFT 16u
#define CSD_Touchpad_Sns__1__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__1__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__1__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__1__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__1__MASK 0x10u
#define CSD_Touchpad_Sns__1__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__1__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__1__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__1__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__1__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__1__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__1__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__1__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__1__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__1__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__1__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__1__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__1__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__1__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__1__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__1__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__1__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__1__PORT 3u
#define CSD_Touchpad_Sns__1__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__1__SHIFT 4
#define CSD_Touchpad_Sns__2__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__2__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__2__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__2__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__2__HSIOM CYREG_HSIOM_PORT_SEL3
#define CSD_Touchpad_Sns__2__HSIOM_MASK 0x00F00000u
#define CSD_Touchpad_Sns__2__HSIOM_SHIFT 20u
#define CSD_Touchpad_Sns__2__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__2__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__2__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__2__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__2__MASK 0x20u
#define CSD_Touchpad_Sns__2__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__2__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__2__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__2__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__2__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__2__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__2__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__2__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__2__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__2__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__2__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__2__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__2__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__2__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__2__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__2__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__2__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__2__PORT 3u
#define CSD_Touchpad_Sns__2__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__2__SHIFT 5
#define CSD_Touchpad_Sns__3__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__3__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__3__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__3__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__3__HSIOM CYREG_HSIOM_PORT_SEL3
#define CSD_Touchpad_Sns__3__HSIOM_MASK 0x0F000000u
#define CSD_Touchpad_Sns__3__HSIOM_SHIFT 24u
#define CSD_Touchpad_Sns__3__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__3__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__3__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__3__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__3__MASK 0x40u
#define CSD_Touchpad_Sns__3__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__3__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__3__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__3__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__3__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__3__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__3__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__3__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__3__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__3__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__3__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__3__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__3__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__3__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__3__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__3__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__3__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__3__PORT 3u
#define CSD_Touchpad_Sns__3__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__3__SHIFT 6
#define CSD_Touchpad_Sns__4__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__4__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__4__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__4__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__4__HSIOM CYREG_HSIOM_PORT_SEL3
#define CSD_Touchpad_Sns__4__HSIOM_MASK 0xF0000000u
#define CSD_Touchpad_Sns__4__HSIOM_SHIFT 28u
#define CSD_Touchpad_Sns__4__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__4__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__4__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__4__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__4__MASK 0x80u
#define CSD_Touchpad_Sns__4__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__4__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__4__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__4__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__4__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__4__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__4__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__4__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__4__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__4__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__4__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__4__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__4__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__4__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__4__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__4__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__4__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__4__PORT 3u
#define CSD_Touchpad_Sns__4__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__4__SHIFT 7
#define CSD_Touchpad_Sns__5__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__5__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__5__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__5__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__5__HSIOM CYREG_HSIOM_PORT_SEL3
#define CSD_Touchpad_Sns__5__HSIOM_MASK 0x00000F00u
#define CSD_Touchpad_Sns__5__HSIOM_SHIFT 8u
#define CSD_Touchpad_Sns__5__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__5__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__5__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__5__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__5__MASK 0x04u
#define CSD_Touchpad_Sns__5__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__5__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__5__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__5__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__5__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__5__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__5__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__5__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__5__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__5__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__5__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__5__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__5__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__5__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__5__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__5__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__5__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__5__PORT 3u
#define CSD_Touchpad_Sns__5__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__5__SHIFT 2
#define CSD_Touchpad_Sns__6__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__6__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__6__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__6__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__6__HSIOM CYREG_HSIOM_PORT_SEL3
#define CSD_Touchpad_Sns__6__HSIOM_MASK 0x000000F0u
#define CSD_Touchpad_Sns__6__HSIOM_SHIFT 4u
#define CSD_Touchpad_Sns__6__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__6__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__6__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__6__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__6__MASK 0x02u
#define CSD_Touchpad_Sns__6__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__6__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__6__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__6__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__6__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__6__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__6__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__6__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__6__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__6__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__6__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__6__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__6__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__6__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__6__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__6__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__6__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__6__PORT 3u
#define CSD_Touchpad_Sns__6__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__6__SHIFT 1
#define CSD_Touchpad_Sns__7__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__7__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__7__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__7__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__7__HSIOM CYREG_HSIOM_PORT_SEL3
#define CSD_Touchpad_Sns__7__HSIOM_MASK 0x0000000Fu
#define CSD_Touchpad_Sns__7__HSIOM_SHIFT 0u
#define CSD_Touchpad_Sns__7__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__7__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__7__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__7__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__7__MASK 0x01u
#define CSD_Touchpad_Sns__7__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__7__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__7__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__7__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__7__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__7__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__7__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__7__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__7__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__7__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__7__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__7__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__7__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__7__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__7__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__7__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__7__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__7__PORT 3u
#define CSD_Touchpad_Sns__7__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__7__SHIFT 0
#define CSD_Touchpad_Sns__8__DR CYREG_GPIO_PRT2_DR
#define CSD_Touchpad_Sns__8__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define CSD_Touchpad_Sns__8__DR_INV CYREG_GPIO_PRT2_DR_INV
#define CSD_Touchpad_Sns__8__DR_SET CYREG_GPIO_PRT2_DR_SET
#define CSD_Touchpad_Sns__8__HSIOM CYREG_HSIOM_PORT_SEL2
#define CSD_Touchpad_Sns__8__HSIOM_MASK 0xF0000000u
#define CSD_Touchpad_Sns__8__HSIOM_SHIFT 28u
#define CSD_Touchpad_Sns__8__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define CSD_Touchpad_Sns__8__INTR CYREG_GPIO_PRT2_INTR
#define CSD_Touchpad_Sns__8__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define CSD_Touchpad_Sns__8__INTSTAT CYREG_GPIO_PRT2_INTR
#define CSD_Touchpad_Sns__8__MASK 0x80u
#define CSD_Touchpad_Sns__8__PA__CFG0 CYREG_UDB_PA2_CFG0
#define CSD_Touchpad_Sns__8__PA__CFG1 CYREG_UDB_PA2_CFG1
#define CSD_Touchpad_Sns__8__PA__CFG10 CYREG_UDB_PA2_CFG10
#define CSD_Touchpad_Sns__8__PA__CFG11 CYREG_UDB_PA2_CFG11
#define CSD_Touchpad_Sns__8__PA__CFG12 CYREG_UDB_PA2_CFG12
#define CSD_Touchpad_Sns__8__PA__CFG13 CYREG_UDB_PA2_CFG13
#define CSD_Touchpad_Sns__8__PA__CFG14 CYREG_UDB_PA2_CFG14
#define CSD_Touchpad_Sns__8__PA__CFG2 CYREG_UDB_PA2_CFG2
#define CSD_Touchpad_Sns__8__PA__CFG3 CYREG_UDB_PA2_CFG3
#define CSD_Touchpad_Sns__8__PA__CFG4 CYREG_UDB_PA2_CFG4
#define CSD_Touchpad_Sns__8__PA__CFG5 CYREG_UDB_PA2_CFG5
#define CSD_Touchpad_Sns__8__PA__CFG6 CYREG_UDB_PA2_CFG6
#define CSD_Touchpad_Sns__8__PA__CFG7 CYREG_UDB_PA2_CFG7
#define CSD_Touchpad_Sns__8__PA__CFG8 CYREG_UDB_PA2_CFG8
#define CSD_Touchpad_Sns__8__PA__CFG9 CYREG_UDB_PA2_CFG9
#define CSD_Touchpad_Sns__8__PC CYREG_GPIO_PRT2_PC
#define CSD_Touchpad_Sns__8__PC2 CYREG_GPIO_PRT2_PC2
#define CSD_Touchpad_Sns__8__PORT 2u
#define CSD_Touchpad_Sns__8__PS CYREG_GPIO_PRT2_PS
#define CSD_Touchpad_Sns__8__SHIFT 7
#define CSD_Touchpad_Sns__9__DR CYREG_GPIO_PRT2_DR
#define CSD_Touchpad_Sns__9__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define CSD_Touchpad_Sns__9__DR_INV CYREG_GPIO_PRT2_DR_INV
#define CSD_Touchpad_Sns__9__DR_SET CYREG_GPIO_PRT2_DR_SET
#define CSD_Touchpad_Sns__9__HSIOM CYREG_HSIOM_PORT_SEL2
#define CSD_Touchpad_Sns__9__HSIOM_MASK 0x0F000000u
#define CSD_Touchpad_Sns__9__HSIOM_SHIFT 24u
#define CSD_Touchpad_Sns__9__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define CSD_Touchpad_Sns__9__INTR CYREG_GPIO_PRT2_INTR
#define CSD_Touchpad_Sns__9__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define CSD_Touchpad_Sns__9__INTSTAT CYREG_GPIO_PRT2_INTR
#define CSD_Touchpad_Sns__9__MASK 0x40u
#define CSD_Touchpad_Sns__9__PA__CFG0 CYREG_UDB_PA2_CFG0
#define CSD_Touchpad_Sns__9__PA__CFG1 CYREG_UDB_PA2_CFG1
#define CSD_Touchpad_Sns__9__PA__CFG10 CYREG_UDB_PA2_CFG10
#define CSD_Touchpad_Sns__9__PA__CFG11 CYREG_UDB_PA2_CFG11
#define CSD_Touchpad_Sns__9__PA__CFG12 CYREG_UDB_PA2_CFG12
#define CSD_Touchpad_Sns__9__PA__CFG13 CYREG_UDB_PA2_CFG13
#define CSD_Touchpad_Sns__9__PA__CFG14 CYREG_UDB_PA2_CFG14
#define CSD_Touchpad_Sns__9__PA__CFG2 CYREG_UDB_PA2_CFG2
#define CSD_Touchpad_Sns__9__PA__CFG3 CYREG_UDB_PA2_CFG3
#define CSD_Touchpad_Sns__9__PA__CFG4 CYREG_UDB_PA2_CFG4
#define CSD_Touchpad_Sns__9__PA__CFG5 CYREG_UDB_PA2_CFG5
#define CSD_Touchpad_Sns__9__PA__CFG6 CYREG_UDB_PA2_CFG6
#define CSD_Touchpad_Sns__9__PA__CFG7 CYREG_UDB_PA2_CFG7
#define CSD_Touchpad_Sns__9__PA__CFG8 CYREG_UDB_PA2_CFG8
#define CSD_Touchpad_Sns__9__PA__CFG9 CYREG_UDB_PA2_CFG9
#define CSD_Touchpad_Sns__9__PC CYREG_GPIO_PRT2_PC
#define CSD_Touchpad_Sns__9__PC2 CYREG_GPIO_PRT2_PC2
#define CSD_Touchpad_Sns__9__PORT 2u
#define CSD_Touchpad_Sns__9__PS CYREG_GPIO_PRT2_PS
#define CSD_Touchpad_Sns__9__SHIFT 6
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__MASK 0x08u
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PORT 3u
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__Trackpad_Col0__TP__SHIFT 3
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__MASK 0x10u
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PORT 3u
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__Trackpad_Col1__TP__SHIFT 4
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__MASK 0x20u
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PORT 3u
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__Trackpad_Col2__TP__SHIFT 5
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__MASK 0x40u
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PORT 3u
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__Trackpad_Col3__TP__SHIFT 6
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__MASK 0x80u
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PORT 3u
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__Trackpad_Col4__TP__SHIFT 7
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__MASK 0x04u
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PORT 3u
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__Trackpad_Row0__TP__SHIFT 2
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__MASK 0x02u
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PORT 3u
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__Trackpad_Row1__TP__SHIFT 1
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__DR CYREG_GPIO_PRT3_DR
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__DR_CLR CYREG_GPIO_PRT3_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__DR_INV CYREG_GPIO_PRT3_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__DR_SET CYREG_GPIO_PRT3_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__INTCFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__INTR CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__INTR_CFG CYREG_GPIO_PRT3_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__INTSTAT CYREG_GPIO_PRT3_INTR
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__MASK 0x01u
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG0 CYREG_UDB_PA3_CFG0
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG1 CYREG_UDB_PA3_CFG1
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG10 CYREG_UDB_PA3_CFG10
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG11 CYREG_UDB_PA3_CFG11
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG12 CYREG_UDB_PA3_CFG12
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG13 CYREG_UDB_PA3_CFG13
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG14 CYREG_UDB_PA3_CFG14
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG2 CYREG_UDB_PA3_CFG2
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG3 CYREG_UDB_PA3_CFG3
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG4 CYREG_UDB_PA3_CFG4
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG5 CYREG_UDB_PA3_CFG5
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG6 CYREG_UDB_PA3_CFG6
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG7 CYREG_UDB_PA3_CFG7
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG8 CYREG_UDB_PA3_CFG8
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PA__CFG9 CYREG_UDB_PA3_CFG9
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PC CYREG_GPIO_PRT3_PC
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PC2 CYREG_GPIO_PRT3_PC2
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PORT 3u
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__PS CYREG_GPIO_PRT3_PS
#define CSD_Touchpad_Sns__Trackpad_Row2__TP__SHIFT 0
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__DR CYREG_GPIO_PRT2_DR
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__DR_INV CYREG_GPIO_PRT2_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__DR_SET CYREG_GPIO_PRT2_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__INTR CYREG_GPIO_PRT2_INTR
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__INTSTAT CYREG_GPIO_PRT2_INTR
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__MASK 0x80u
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG0 CYREG_UDB_PA2_CFG0
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG1 CYREG_UDB_PA2_CFG1
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG10 CYREG_UDB_PA2_CFG10
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG11 CYREG_UDB_PA2_CFG11
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG12 CYREG_UDB_PA2_CFG12
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG13 CYREG_UDB_PA2_CFG13
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG14 CYREG_UDB_PA2_CFG14
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG2 CYREG_UDB_PA2_CFG2
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG3 CYREG_UDB_PA2_CFG3
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG4 CYREG_UDB_PA2_CFG4
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG5 CYREG_UDB_PA2_CFG5
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG6 CYREG_UDB_PA2_CFG6
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG7 CYREG_UDB_PA2_CFG7
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG8 CYREG_UDB_PA2_CFG8
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PA__CFG9 CYREG_UDB_PA2_CFG9
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PC CYREG_GPIO_PRT2_PC
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PC2 CYREG_GPIO_PRT2_PC2
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PORT 2u
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__PS CYREG_GPIO_PRT2_PS
#define CSD_Touchpad_Sns__Trackpad_Row3__TP__SHIFT 7
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__DR CYREG_GPIO_PRT2_DR
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__DR_CLR CYREG_GPIO_PRT2_DR_CLR
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__DR_INV CYREG_GPIO_PRT2_DR_INV
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__DR_SET CYREG_GPIO_PRT2_DR_SET
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__INTCFG CYREG_GPIO_PRT2_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__INTR CYREG_GPIO_PRT2_INTR
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__INTR_CFG CYREG_GPIO_PRT2_INTR_CFG
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__INTSTAT CYREG_GPIO_PRT2_INTR
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__MASK 0x40u
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG0 CYREG_UDB_PA2_CFG0
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG1 CYREG_UDB_PA2_CFG1
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG10 CYREG_UDB_PA2_CFG10
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG11 CYREG_UDB_PA2_CFG11
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG12 CYREG_UDB_PA2_CFG12
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG13 CYREG_UDB_PA2_CFG13
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG14 CYREG_UDB_PA2_CFG14
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG2 CYREG_UDB_PA2_CFG2
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG3 CYREG_UDB_PA2_CFG3
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG4 CYREG_UDB_PA2_CFG4
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG5 CYREG_UDB_PA2_CFG5
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG6 CYREG_UDB_PA2_CFG6
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG7 CYREG_UDB_PA2_CFG7
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG8 CYREG_UDB_PA2_CFG8
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PA__CFG9 CYREG_UDB_PA2_CFG9
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PC CYREG_GPIO_PRT2_PC
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PC2 CYREG_GPIO_PRT2_PC2
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PORT 2u
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__PS CYREG_GPIO_PRT2_PS
#define CSD_Touchpad_Sns__Trackpad_Row4__TP__SHIFT 6

/* Keyboard_Rows */
#define Keyboard_Rows__0__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Rows__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Rows__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Rows__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Rows__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define Keyboard_Rows__0__HSIOM_MASK 0x0000F000u
#define Keyboard_Rows__0__HSIOM_SHIFT 12u
#define Keyboard_Rows__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__0__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__0__MASK 0x08u
#define Keyboard_Rows__0__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Rows__0__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Rows__0__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Rows__0__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Rows__0__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Rows__0__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Rows__0__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Rows__0__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Rows__0__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Rows__0__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Rows__0__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Rows__0__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Rows__0__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Rows__0__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Rows__0__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Rows__0__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Rows__0__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Rows__0__PORT 1u
#define Keyboard_Rows__0__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Rows__0__SHIFT 3
#define Keyboard_Rows__1__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Rows__1__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Rows__1__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Rows__1__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Rows__1__HSIOM CYREG_HSIOM_PORT_SEL1
#define Keyboard_Rows__1__HSIOM_MASK 0x000F0000u
#define Keyboard_Rows__1__HSIOM_SHIFT 16u
#define Keyboard_Rows__1__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__1__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__1__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__1__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__1__MASK 0x10u
#define Keyboard_Rows__1__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Rows__1__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Rows__1__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Rows__1__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Rows__1__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Rows__1__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Rows__1__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Rows__1__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Rows__1__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Rows__1__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Rows__1__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Rows__1__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Rows__1__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Rows__1__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Rows__1__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Rows__1__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Rows__1__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Rows__1__PORT 1u
#define Keyboard_Rows__1__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Rows__1__SHIFT 4
#define Keyboard_Rows__2__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Rows__2__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Rows__2__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Rows__2__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Rows__2__HSIOM CYREG_HSIOM_PORT_SEL1
#define Keyboard_Rows__2__HSIOM_MASK 0x00F00000u
#define Keyboard_Rows__2__HSIOM_SHIFT 20u
#define Keyboard_Rows__2__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__2__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__2__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__2__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__2__MASK 0x20u
#define Keyboard_Rows__2__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Rows__2__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Rows__2__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Rows__2__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Rows__2__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Rows__2__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Rows__2__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Rows__2__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Rows__2__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Rows__2__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Rows__2__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Rows__2__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Rows__2__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Rows__2__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Rows__2__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Rows__2__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Rows__2__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Rows__2__PORT 1u
#define Keyboard_Rows__2__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Rows__2__SHIFT 5
#define Keyboard_Rows__3__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Rows__3__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Rows__3__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Rows__3__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Rows__3__HSIOM CYREG_HSIOM_PORT_SEL1
#define Keyboard_Rows__3__HSIOM_MASK 0x0F000000u
#define Keyboard_Rows__3__HSIOM_SHIFT 24u
#define Keyboard_Rows__3__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__3__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__3__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__3__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__3__MASK 0x40u
#define Keyboard_Rows__3__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Rows__3__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Rows__3__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Rows__3__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Rows__3__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Rows__3__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Rows__3__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Rows__3__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Rows__3__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Rows__3__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Rows__3__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Rows__3__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Rows__3__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Rows__3__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Rows__3__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Rows__3__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Rows__3__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Rows__3__PORT 1u
#define Keyboard_Rows__3__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Rows__3__SHIFT 6
#define Keyboard_Rows__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Rows__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Rows__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Rows__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Rows__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Rows__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Rows__MASK 0x78u
#define Keyboard_Rows__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Rows__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Rows__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Rows__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Rows__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Rows__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Rows__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Rows__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Rows__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Rows__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Rows__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Rows__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Rows__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Rows__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Rows__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Rows__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Rows__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Rows__PORT 1u
#define Keyboard_Rows__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Rows__SHIFT 3

/* Keyboard_Columns */
#define Keyboard_Columns__0__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Columns__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Columns__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Columns__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Columns__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define Keyboard_Columns__0__HSIOM_MASK 0x0000000Fu
#define Keyboard_Columns__0__HSIOM_SHIFT 0u
#define Keyboard_Columns__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Columns__0__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Columns__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Columns__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Columns__0__MASK 0x01u
#define Keyboard_Columns__0__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Columns__0__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Columns__0__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Columns__0__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Columns__0__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Columns__0__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Columns__0__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Columns__0__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Columns__0__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Columns__0__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Columns__0__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Columns__0__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Columns__0__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Columns__0__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Columns__0__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Columns__0__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Columns__0__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Columns__0__PORT 1u
#define Keyboard_Columns__0__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Columns__0__SHIFT 0
#define Keyboard_Columns__1__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Columns__1__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Columns__1__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Columns__1__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Columns__1__HSIOM CYREG_HSIOM_PORT_SEL1
#define Keyboard_Columns__1__HSIOM_MASK 0x000000F0u
#define Keyboard_Columns__1__HSIOM_SHIFT 4u
#define Keyboard_Columns__1__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Columns__1__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Columns__1__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Columns__1__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Columns__1__MASK 0x02u
#define Keyboard_Columns__1__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Columns__1__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Columns__1__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Columns__1__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Columns__1__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Columns__1__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Columns__1__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Columns__1__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Columns__1__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Columns__1__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Columns__1__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Columns__1__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Columns__1__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Columns__1__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Columns__1__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Columns__1__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Columns__1__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Columns__1__PORT 1u
#define Keyboard_Columns__1__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Columns__1__SHIFT 1
#define Keyboard_Columns__2__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Columns__2__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Columns__2__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Columns__2__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Columns__2__HSIOM CYREG_HSIOM_PORT_SEL1
#define Keyboard_Columns__2__HSIOM_MASK 0x00000F00u
#define Keyboard_Columns__2__HSIOM_SHIFT 8u
#define Keyboard_Columns__2__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Columns__2__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Columns__2__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Columns__2__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Columns__2__MASK 0x04u
#define Keyboard_Columns__2__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Columns__2__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Columns__2__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Columns__2__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Columns__2__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Columns__2__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Columns__2__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Columns__2__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Columns__2__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Columns__2__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Columns__2__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Columns__2__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Columns__2__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Columns__2__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Columns__2__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Columns__2__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Columns__2__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Columns__2__PORT 1u
#define Keyboard_Columns__2__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Columns__2__SHIFT 2
#define Keyboard_Columns__DR CYREG_GPIO_PRT1_DR
#define Keyboard_Columns__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define Keyboard_Columns__DR_INV CYREG_GPIO_PRT1_DR_INV
#define Keyboard_Columns__DR_SET CYREG_GPIO_PRT1_DR_SET
#define Keyboard_Columns__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Columns__INTR CYREG_GPIO_PRT1_INTR
#define Keyboard_Columns__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define Keyboard_Columns__INTSTAT CYREG_GPIO_PRT1_INTR
#define Keyboard_Columns__MASK 0x07u
#define Keyboard_Columns__PA__CFG0 CYREG_UDB_PA1_CFG0
#define Keyboard_Columns__PA__CFG1 CYREG_UDB_PA1_CFG1
#define Keyboard_Columns__PA__CFG10 CYREG_UDB_PA1_CFG10
#define Keyboard_Columns__PA__CFG11 CYREG_UDB_PA1_CFG11
#define Keyboard_Columns__PA__CFG12 CYREG_UDB_PA1_CFG12
#define Keyboard_Columns__PA__CFG13 CYREG_UDB_PA1_CFG13
#define Keyboard_Columns__PA__CFG14 CYREG_UDB_PA1_CFG14
#define Keyboard_Columns__PA__CFG2 CYREG_UDB_PA1_CFG2
#define Keyboard_Columns__PA__CFG3 CYREG_UDB_PA1_CFG3
#define Keyboard_Columns__PA__CFG4 CYREG_UDB_PA1_CFG4
#define Keyboard_Columns__PA__CFG5 CYREG_UDB_PA1_CFG5
#define Keyboard_Columns__PA__CFG6 CYREG_UDB_PA1_CFG6
#define Keyboard_Columns__PA__CFG7 CYREG_UDB_PA1_CFG7
#define Keyboard_Columns__PA__CFG8 CYREG_UDB_PA1_CFG8
#define Keyboard_Columns__PA__CFG9 CYREG_UDB_PA1_CFG9
#define Keyboard_Columns__PC CYREG_GPIO_PRT1_PC
#define Keyboard_Columns__PC2 CYREG_GPIO_PRT1_PC2
#define Keyboard_Columns__PORT 1u
#define Keyboard_Columns__PS CYREG_GPIO_PRT1_PS
#define Keyboard_Columns__SHIFT 0
#define Keyboard_Columns__SNAP CYREG_GPIO_PRT1_INTR

/* Keyboard_Columns_Interrupt */
#define Keyboard_Columns_Interrupt__INTC_CLR_EN_REG CYREG_CM0_ICER
#define Keyboard_Columns_Interrupt__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define Keyboard_Columns_Interrupt__INTC_MASK 0x02u
#define Keyboard_Columns_Interrupt__INTC_NUMBER 1u
#define Keyboard_Columns_Interrupt__INTC_PRIOR_MASK 0xC000u
#define Keyboard_Columns_Interrupt__INTC_PRIOR_NUM 3u
#define Keyboard_Columns_Interrupt__INTC_PRIOR_REG CYREG_CM0_IPR0
#define Keyboard_Columns_Interrupt__INTC_SET_EN_REG CYREG_CM0_ISER
#define Keyboard_Columns_Interrupt__INTC_SET_PD_REG CYREG_CM0_ISPR

/* Timer_HW_Clock_1 */
#define Timer_HW_Clock_1__CTRL_REGISTER CYREG_PERI_PCLK_CTL7
#define Timer_HW_Clock_1__DIV_ID 0x00000042u
#define Timer_HW_Clock_1__DIV_REGISTER CYREG_PERI_DIV_16_CTL2
#define Timer_HW_Clock_1__PA_DIV_ID 0x000000FFu

/* Motion_Sensor_I2C_SCB */
#define Motion_Sensor_I2C_SCB__CTRL CYREG_SCB1_CTRL
#define Motion_Sensor_I2C_SCB__EZ_DATA0 CYREG_SCB1_EZ_DATA0
#define Motion_Sensor_I2C_SCB__EZ_DATA1 CYREG_SCB1_EZ_DATA1
#define Motion_Sensor_I2C_SCB__EZ_DATA10 CYREG_SCB1_EZ_DATA10
#define Motion_Sensor_I2C_SCB__EZ_DATA11 CYREG_SCB1_EZ_DATA11
#define Motion_Sensor_I2C_SCB__EZ_DATA12 CYREG_SCB1_EZ_DATA12
#define Motion_Sensor_I2C_SCB__EZ_DATA13 CYREG_SCB1_EZ_DATA13
#define Motion_Sensor_I2C_SCB__EZ_DATA14 CYREG_SCB1_EZ_DATA14
#define Motion_Sensor_I2C_SCB__EZ_DATA15 CYREG_SCB1_EZ_DATA15
#define Motion_Sensor_I2C_SCB__EZ_DATA16 CYREG_SCB1_EZ_DATA16
#define Motion_Sensor_I2C_SCB__EZ_DATA17 CYREG_SCB1_EZ_DATA17
#define Motion_Sensor_I2C_SCB__EZ_DATA18 CYREG_SCB1_EZ_DATA18
#define Motion_Sensor_I2C_SCB__EZ_DATA19 CYREG_SCB1_EZ_DATA19
#define Motion_Sensor_I2C_SCB__EZ_DATA2 CYREG_SCB1_EZ_DATA2
#define Motion_Sensor_I2C_SCB__EZ_DATA20 CYREG_SCB1_EZ_DATA20
#define Motion_Sensor_I2C_SCB__EZ_DATA21 CYREG_SCB1_EZ_DATA21
#define Motion_Sensor_I2C_SCB__EZ_DATA22 CYREG_SCB1_EZ_DATA22
#define Motion_Sensor_I2C_SCB__EZ_DATA23 CYREG_SCB1_EZ_DATA23
#define Motion_Sensor_I2C_SCB__EZ_DATA24 CYREG_SCB1_EZ_DATA24
#define Motion_Sensor_I2C_SCB__EZ_DATA25 CYREG_SCB1_EZ_DATA25
#define Motion_Sensor_I2C_SCB__EZ_DATA26 CYREG_SCB1_EZ_DATA26
#define Motion_Sensor_I2C_SCB__EZ_DATA27 CYREG_SCB1_EZ_DATA27
#define Motion_Sensor_I2C_SCB__EZ_DATA28 CYREG_SCB1_EZ_DATA28
#define Motion_Sensor_I2C_SCB__EZ_DATA29 CYREG_SCB1_EZ_DATA29
#define Motion_Sensor_I2C_SCB__EZ_DATA3 CYREG_SCB1_EZ_DATA3
#define Motion_Sensor_I2C_SCB__EZ_DATA30 CYREG_SCB1_EZ_DATA30
#define Motion_Sensor_I2C_SCB__EZ_DATA31 CYREG_SCB1_EZ_DATA31
#define Motion_Sensor_I2C_SCB__EZ_DATA4 CYREG_SCB1_EZ_DATA4
#define Motion_Sensor_I2C_SCB__EZ_DATA5 CYREG_SCB1_EZ_DATA5
#define Motion_Sensor_I2C_SCB__EZ_DATA6 CYREG_SCB1_EZ_DATA6
#define Motion_Sensor_I2C_SCB__EZ_DATA7 CYREG_SCB1_EZ_DATA7
#define Motion_Sensor_I2C_SCB__EZ_DATA8 CYREG_SCB1_EZ_DATA8
#define Motion_Sensor_I2C_SCB__EZ_DATA9 CYREG_SCB1_EZ_DATA9
#define Motion_Sensor_I2C_SCB__I2C_CFG CYREG_SCB1_I2C_CFG
#define Motion_Sensor_I2C_SCB__I2C_CTRL CYREG_SCB1_I2C_CTRL
#define Motion_Sensor_I2C_SCB__I2C_M_CMD CYREG_SCB1_I2C_M_CMD
#define Motion_Sensor_I2C_SCB__I2C_S_CMD CYREG_SCB1_I2C_S_CMD
#define Motion_Sensor_I2C_SCB__I2C_STATUS CYREG_SCB1_I2C_STATUS
#define Motion_Sensor_I2C_SCB__INTR_CAUSE CYREG_SCB1_INTR_CAUSE
#define Motion_Sensor_I2C_SCB__INTR_I2C_EC CYREG_SCB1_INTR_I2C_EC
#define Motion_Sensor_I2C_SCB__INTR_I2C_EC_MASK CYREG_SCB1_INTR_I2C_EC_MASK
#define Motion_Sensor_I2C_SCB__INTR_I2C_EC_MASKED CYREG_SCB1_INTR_I2C_EC_MASKED
#define Motion_Sensor_I2C_SCB__INTR_M CYREG_SCB1_INTR_M
#define Motion_Sensor_I2C_SCB__INTR_M_MASK CYREG_SCB1_INTR_M_MASK
#define Motion_Sensor_I2C_SCB__INTR_M_MASKED CYREG_SCB1_INTR_M_MASKED
#define Motion_Sensor_I2C_SCB__INTR_M_SET CYREG_SCB1_INTR_M_SET
#define Motion_Sensor_I2C_SCB__INTR_RX CYREG_SCB1_INTR_RX
#define Motion_Sensor_I2C_SCB__INTR_RX_MASK CYREG_SCB1_INTR_RX_MASK
#define Motion_Sensor_I2C_SCB__INTR_RX_MASKED CYREG_SCB1_INTR_RX_MASKED
#define Motion_Sensor_I2C_SCB__INTR_RX_SET CYREG_SCB1_INTR_RX_SET
#define Motion_Sensor_I2C_SCB__INTR_S CYREG_SCB1_INTR_S
#define Motion_Sensor_I2C_SCB__INTR_S_MASK CYREG_SCB1_INTR_S_MASK
#define Motion_Sensor_I2C_SCB__INTR_S_MASKED CYREG_SCB1_INTR_S_MASKED
#define Motion_Sensor_I2C_SCB__INTR_S_SET CYREG_SCB1_INTR_S_SET
#define Motion_Sensor_I2C_SCB__INTR_SPI_EC CYREG_SCB1_INTR_SPI_EC
#define Motion_Sensor_I2C_SCB__INTR_SPI_EC_MASK CYREG_SCB1_INTR_SPI_EC_MASK
#define Motion_Sensor_I2C_SCB__INTR_SPI_EC_MASKED CYREG_SCB1_INTR_SPI_EC_MASKED
#define Motion_Sensor_I2C_SCB__INTR_TX CYREG_SCB1_INTR_TX
#define Motion_Sensor_I2C_SCB__INTR_TX_MASK CYREG_SCB1_INTR_TX_MASK
#define Motion_Sensor_I2C_SCB__INTR_TX_MASKED CYREG_SCB1_INTR_TX_MASKED
#define Motion_Sensor_I2C_SCB__INTR_TX_SET CYREG_SCB1_INTR_TX_SET
#define Motion_Sensor_I2C_SCB__RX_CTRL CYREG_SCB1_RX_CTRL
#define Motion_Sensor_I2C_SCB__RX_FIFO_CTRL CYREG_SCB1_RX_FIFO_CTRL
#define Motion_Sensor_I2C_SCB__RX_FIFO_RD CYREG_SCB1_RX_FIFO_RD
#define Motion_Sensor_I2C_SCB__RX_FIFO_RD_SILENT CYREG_SCB1_RX_FIFO_RD_SILENT
#define Motion_Sensor_I2C_SCB__RX_FIFO_STATUS CYREG_SCB1_RX_FIFO_STATUS
#define Motion_Sensor_I2C_SCB__RX_MATCH CYREG_SCB1_RX_MATCH
#define Motion_Sensor_I2C_SCB__SPI_CTRL CYREG_SCB1_SPI_CTRL
#define Motion_Sensor_I2C_SCB__SPI_STATUS CYREG_SCB1_SPI_STATUS
#define Motion_Sensor_I2C_SCB__SS0_POSISTION 0u
#define Motion_Sensor_I2C_SCB__SS1_POSISTION 1u
#define Motion_Sensor_I2C_SCB__SS2_POSISTION 2u
#define Motion_Sensor_I2C_SCB__SS3_POSISTION 3u
#define Motion_Sensor_I2C_SCB__STATUS CYREG_SCB1_STATUS
#define Motion_Sensor_I2C_SCB__TX_CTRL CYREG_SCB1_TX_CTRL
#define Motion_Sensor_I2C_SCB__TX_FIFO_CTRL CYREG_SCB1_TX_FIFO_CTRL
#define Motion_Sensor_I2C_SCB__TX_FIFO_STATUS CYREG_SCB1_TX_FIFO_STATUS
#define Motion_Sensor_I2C_SCB__TX_FIFO_WR CYREG_SCB1_TX_FIFO_WR
#define Motion_Sensor_I2C_SCB__UART_CTRL CYREG_SCB1_UART_CTRL
#define Motion_Sensor_I2C_SCB__UART_FLOW_CTRL CYREG_SCB1_UART_FLOW_CTRL
#define Motion_Sensor_I2C_SCB__UART_RX_CTRL CYREG_SCB1_UART_RX_CTRL
#define Motion_Sensor_I2C_SCB__UART_RX_STATUS CYREG_SCB1_UART_RX_STATUS
#define Motion_Sensor_I2C_SCB__UART_TX_CTRL CYREG_SCB1_UART_TX_CTRL

/* Motion_Sensor_I2C_SCB_IRQ */
#define Motion_Sensor_I2C_SCB_IRQ__INTC_CLR_EN_REG CYREG_CM0_ICER
#define Motion_Sensor_I2C_SCB_IRQ__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define Motion_Sensor_I2C_SCB_IRQ__INTC_MASK 0x400u
#define Motion_Sensor_I2C_SCB_IRQ__INTC_NUMBER 10u
#define Motion_Sensor_I2C_SCB_IRQ__INTC_PRIOR_MASK 0xC00000u
#define Motion_Sensor_I2C_SCB_IRQ__INTC_PRIOR_NUM 3u
#define Motion_Sensor_I2C_SCB_IRQ__INTC_PRIOR_REG CYREG_CM0_IPR2
#define Motion_Sensor_I2C_SCB_IRQ__INTC_SET_EN_REG CYREG_CM0_ISER
#define Motion_Sensor_I2C_SCB_IRQ__INTC_SET_PD_REG CYREG_CM0_ISPR

/* Motion_Sensor_I2C_SCBCLK */
#define Motion_Sensor_I2C_SCBCLK__CTRL_REGISTER CYREG_PERI_PCLK_CTL2
#define Motion_Sensor_I2C_SCBCLK__DIV_ID 0x00000044u
#define Motion_Sensor_I2C_SCBCLK__DIV_REGISTER CYREG_PERI_DIV_16_CTL4
#define Motion_Sensor_I2C_SCBCLK__PA_DIV_ID 0x000000FFu

/* Motion_Sensor_I2C_scl */
#define Motion_Sensor_I2C_scl__0__DR CYREG_GPIO_PRT0_DR
#define Motion_Sensor_I2C_scl__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define Motion_Sensor_I2C_scl__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define Motion_Sensor_I2C_scl__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define Motion_Sensor_I2C_scl__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define Motion_Sensor_I2C_scl__0__HSIOM_MASK 0x000000F0u
#define Motion_Sensor_I2C_scl__0__HSIOM_SHIFT 4u
#define Motion_Sensor_I2C_scl__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_I2C_scl__0__INTR CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_I2C_scl__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_I2C_scl__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_I2C_scl__0__MASK 0x02u
#define Motion_Sensor_I2C_scl__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define Motion_Sensor_I2C_scl__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define Motion_Sensor_I2C_scl__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define Motion_Sensor_I2C_scl__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define Motion_Sensor_I2C_scl__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define Motion_Sensor_I2C_scl__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define Motion_Sensor_I2C_scl__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define Motion_Sensor_I2C_scl__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define Motion_Sensor_I2C_scl__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define Motion_Sensor_I2C_scl__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define Motion_Sensor_I2C_scl__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define Motion_Sensor_I2C_scl__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define Motion_Sensor_I2C_scl__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define Motion_Sensor_I2C_scl__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define Motion_Sensor_I2C_scl__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define Motion_Sensor_I2C_scl__0__PC CYREG_GPIO_PRT0_PC
#define Motion_Sensor_I2C_scl__0__PC2 CYREG_GPIO_PRT0_PC2
#define Motion_Sensor_I2C_scl__0__PORT 0u
#define Motion_Sensor_I2C_scl__0__PS CYREG_GPIO_PRT0_PS
#define Motion_Sensor_I2C_scl__0__SHIFT 1
#define Motion_Sensor_I2C_scl__DR CYREG_GPIO_PRT0_DR
#define Motion_Sensor_I2C_scl__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define Motion_Sensor_I2C_scl__DR_INV CYREG_GPIO_PRT0_DR_INV
#define Motion_Sensor_I2C_scl__DR_SET CYREG_GPIO_PRT0_DR_SET
#define Motion_Sensor_I2C_scl__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_I2C_scl__INTR CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_I2C_scl__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_I2C_scl__INTSTAT CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_I2C_scl__MASK 0x02u
#define Motion_Sensor_I2C_scl__PA__CFG0 CYREG_UDB_PA0_CFG0
#define Motion_Sensor_I2C_scl__PA__CFG1 CYREG_UDB_PA0_CFG1
#define Motion_Sensor_I2C_scl__PA__CFG10 CYREG_UDB_PA0_CFG10
#define Motion_Sensor_I2C_scl__PA__CFG11 CYREG_UDB_PA0_CFG11
#define Motion_Sensor_I2C_scl__PA__CFG12 CYREG_UDB_PA0_CFG12
#define Motion_Sensor_I2C_scl__PA__CFG13 CYREG_UDB_PA0_CFG13
#define Motion_Sensor_I2C_scl__PA__CFG14 CYREG_UDB_PA0_CFG14
#define Motion_Sensor_I2C_scl__PA__CFG2 CYREG_UDB_PA0_CFG2
#define Motion_Sensor_I2C_scl__PA__CFG3 CYREG_UDB_PA0_CFG3
#define Motion_Sensor_I2C_scl__PA__CFG4 CYREG_UDB_PA0_CFG4
#define Motion_Sensor_I2C_scl__PA__CFG5 CYREG_UDB_PA0_CFG5
#define Motion_Sensor_I2C_scl__PA__CFG6 CYREG_UDB_PA0_CFG6
#define Motion_Sensor_I2C_scl__PA__CFG7 CYREG_UDB_PA0_CFG7
#define Motion_Sensor_I2C_scl__PA__CFG8 CYREG_UDB_PA0_CFG8
#define Motion_Sensor_I2C_scl__PA__CFG9 CYREG_UDB_PA0_CFG9
#define Motion_Sensor_I2C_scl__PC CYREG_GPIO_PRT0_PC
#define Motion_Sensor_I2C_scl__PC2 CYREG_GPIO_PRT0_PC2
#define Motion_Sensor_I2C_scl__PORT 0u
#define Motion_Sensor_I2C_scl__PS CYREG_GPIO_PRT0_PS
#define Motion_Sensor_I2C_scl__SHIFT 1

/* Motion_Sensor_I2C_sda */
#define Motion_Sensor_I2C_sda__0__DR CYREG_GPIO_PRT0_DR
#define Motion_Sensor_I2C_sda__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define Motion_Sensor_I2C_sda__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define Motion_Sensor_I2C_sda__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define Motion_Sensor_I2C_sda__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define Motion_Sensor_I2C_sda__0__HSIOM_MASK 0x0000000Fu
#define Motion_Sensor_I2C_sda__0__HSIOM_SHIFT 0u
#define Motion_Sensor_I2C_sda__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_I2C_sda__0__INTR CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_I2C_sda__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_I2C_sda__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_I2C_sda__0__MASK 0x01u
#define Motion_Sensor_I2C_sda__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define Motion_Sensor_I2C_sda__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define Motion_Sensor_I2C_sda__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define Motion_Sensor_I2C_sda__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define Motion_Sensor_I2C_sda__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define Motion_Sensor_I2C_sda__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define Motion_Sensor_I2C_sda__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define Motion_Sensor_I2C_sda__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define Motion_Sensor_I2C_sda__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define Motion_Sensor_I2C_sda__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define Motion_Sensor_I2C_sda__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define Motion_Sensor_I2C_sda__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define Motion_Sensor_I2C_sda__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define Motion_Sensor_I2C_sda__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define Motion_Sensor_I2C_sda__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define Motion_Sensor_I2C_sda__0__PC CYREG_GPIO_PRT0_PC
#define Motion_Sensor_I2C_sda__0__PC2 CYREG_GPIO_PRT0_PC2
#define Motion_Sensor_I2C_sda__0__PORT 0u
#define Motion_Sensor_I2C_sda__0__PS CYREG_GPIO_PRT0_PS
#define Motion_Sensor_I2C_sda__0__SHIFT 0
#define Motion_Sensor_I2C_sda__DR CYREG_GPIO_PRT0_DR
#define Motion_Sensor_I2C_sda__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define Motion_Sensor_I2C_sda__DR_INV CYREG_GPIO_PRT0_DR_INV
#define Motion_Sensor_I2C_sda__DR_SET CYREG_GPIO_PRT0_DR_SET
#define Motion_Sensor_I2C_sda__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_I2C_sda__INTR CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_I2C_sda__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_I2C_sda__INTSTAT CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_I2C_sda__MASK 0x01u
#define Motion_Sensor_I2C_sda__PA__CFG0 CYREG_UDB_PA0_CFG0
#define Motion_Sensor_I2C_sda__PA__CFG1 CYREG_UDB_PA0_CFG1
#define Motion_Sensor_I2C_sda__PA__CFG10 CYREG_UDB_PA0_CFG10
#define Motion_Sensor_I2C_sda__PA__CFG11 CYREG_UDB_PA0_CFG11
#define Motion_Sensor_I2C_sda__PA__CFG12 CYREG_UDB_PA0_CFG12
#define Motion_Sensor_I2C_sda__PA__CFG13 CYREG_UDB_PA0_CFG13
#define Motion_Sensor_I2C_sda__PA__CFG14 CYREG_UDB_PA0_CFG14
#define Motion_Sensor_I2C_sda__PA__CFG2 CYREG_UDB_PA0_CFG2
#define Motion_Sensor_I2C_sda__PA__CFG3 CYREG_UDB_PA0_CFG3
#define Motion_Sensor_I2C_sda__PA__CFG4 CYREG_UDB_PA0_CFG4
#define Motion_Sensor_I2C_sda__PA__CFG5 CYREG_UDB_PA0_CFG5
#define Motion_Sensor_I2C_sda__PA__CFG6 CYREG_UDB_PA0_CFG6
#define Motion_Sensor_I2C_sda__PA__CFG7 CYREG_UDB_PA0_CFG7
#define Motion_Sensor_I2C_sda__PA__CFG8 CYREG_UDB_PA0_CFG8
#define Motion_Sensor_I2C_sda__PA__CFG9 CYREG_UDB_PA0_CFG9
#define Motion_Sensor_I2C_sda__PC CYREG_GPIO_PRT0_PC
#define Motion_Sensor_I2C_sda__PC2 CYREG_GPIO_PRT0_PC2
#define Motion_Sensor_I2C_sda__PORT 0u
#define Motion_Sensor_I2C_sda__PS CYREG_GPIO_PRT0_PS
#define Motion_Sensor_I2C_sda__SHIFT 0

/* Timer_HW_Interrupt_1 */
#define Timer_HW_Interrupt_1__INTC_CLR_EN_REG CYREG_CM0_ICER
#define Timer_HW_Interrupt_1__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define Timer_HW_Interrupt_1__INTC_MASK 0x20000u
#define Timer_HW_Interrupt_1__INTC_NUMBER 17u
#define Timer_HW_Interrupt_1__INTC_PRIOR_MASK 0xC000u
#define Timer_HW_Interrupt_1__INTC_PRIOR_NUM 3u
#define Timer_HW_Interrupt_1__INTC_PRIOR_REG CYREG_CM0_IPR4
#define Timer_HW_Interrupt_1__INTC_SET_EN_REG CYREG_CM0_ISER
#define Timer_HW_Interrupt_1__INTC_SET_PD_REG CYREG_CM0_ISPR

/* BatteryEn_Voice_Button */
#define BatteryEn_Voice_Button__0__DR CYREG_GPIO_PRT1_DR
#define BatteryEn_Voice_Button__0__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define BatteryEn_Voice_Button__0__DR_INV CYREG_GPIO_PRT1_DR_INV
#define BatteryEn_Voice_Button__0__DR_SET CYREG_GPIO_PRT1_DR_SET
#define BatteryEn_Voice_Button__0__HSIOM CYREG_HSIOM_PORT_SEL1
#define BatteryEn_Voice_Button__0__HSIOM_MASK 0xF0000000u
#define BatteryEn_Voice_Button__0__HSIOM_SHIFT 28u
#define BatteryEn_Voice_Button__0__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define BatteryEn_Voice_Button__0__INTR CYREG_GPIO_PRT1_INTR
#define BatteryEn_Voice_Button__0__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define BatteryEn_Voice_Button__0__INTSTAT CYREG_GPIO_PRT1_INTR
#define BatteryEn_Voice_Button__0__MASK 0x80u
#define BatteryEn_Voice_Button__0__PA__CFG0 CYREG_UDB_PA1_CFG0
#define BatteryEn_Voice_Button__0__PA__CFG1 CYREG_UDB_PA1_CFG1
#define BatteryEn_Voice_Button__0__PA__CFG10 CYREG_UDB_PA1_CFG10
#define BatteryEn_Voice_Button__0__PA__CFG11 CYREG_UDB_PA1_CFG11
#define BatteryEn_Voice_Button__0__PA__CFG12 CYREG_UDB_PA1_CFG12
#define BatteryEn_Voice_Button__0__PA__CFG13 CYREG_UDB_PA1_CFG13
#define BatteryEn_Voice_Button__0__PA__CFG14 CYREG_UDB_PA1_CFG14
#define BatteryEn_Voice_Button__0__PA__CFG2 CYREG_UDB_PA1_CFG2
#define BatteryEn_Voice_Button__0__PA__CFG3 CYREG_UDB_PA1_CFG3
#define BatteryEn_Voice_Button__0__PA__CFG4 CYREG_UDB_PA1_CFG4
#define BatteryEn_Voice_Button__0__PA__CFG5 CYREG_UDB_PA1_CFG5
#define BatteryEn_Voice_Button__0__PA__CFG6 CYREG_UDB_PA1_CFG6
#define BatteryEn_Voice_Button__0__PA__CFG7 CYREG_UDB_PA1_CFG7
#define BatteryEn_Voice_Button__0__PA__CFG8 CYREG_UDB_PA1_CFG8
#define BatteryEn_Voice_Button__0__PA__CFG9 CYREG_UDB_PA1_CFG9
#define BatteryEn_Voice_Button__0__PC CYREG_GPIO_PRT1_PC
#define BatteryEn_Voice_Button__0__PC2 CYREG_GPIO_PRT1_PC2
#define BatteryEn_Voice_Button__0__PORT 1u
#define BatteryEn_Voice_Button__0__PS CYREG_GPIO_PRT1_PS
#define BatteryEn_Voice_Button__0__SHIFT 7
#define BatteryEn_Voice_Button__DR CYREG_GPIO_PRT1_DR
#define BatteryEn_Voice_Button__DR_CLR CYREG_GPIO_PRT1_DR_CLR
#define BatteryEn_Voice_Button__DR_INV CYREG_GPIO_PRT1_DR_INV
#define BatteryEn_Voice_Button__DR_SET CYREG_GPIO_PRT1_DR_SET
#define BatteryEn_Voice_Button__INTCFG CYREG_GPIO_PRT1_INTR_CFG
#define BatteryEn_Voice_Button__INTR CYREG_GPIO_PRT1_INTR
#define BatteryEn_Voice_Button__INTR_CFG CYREG_GPIO_PRT1_INTR_CFG
#define BatteryEn_Voice_Button__INTSTAT CYREG_GPIO_PRT1_INTR
#define BatteryEn_Voice_Button__MASK 0x80u
#define BatteryEn_Voice_Button__PA__CFG0 CYREG_UDB_PA1_CFG0
#define BatteryEn_Voice_Button__PA__CFG1 CYREG_UDB_PA1_CFG1
#define BatteryEn_Voice_Button__PA__CFG10 CYREG_UDB_PA1_CFG10
#define BatteryEn_Voice_Button__PA__CFG11 CYREG_UDB_PA1_CFG11
#define BatteryEn_Voice_Button__PA__CFG12 CYREG_UDB_PA1_CFG12
#define BatteryEn_Voice_Button__PA__CFG13 CYREG_UDB_PA1_CFG13
#define BatteryEn_Voice_Button__PA__CFG14 CYREG_UDB_PA1_CFG14
#define BatteryEn_Voice_Button__PA__CFG2 CYREG_UDB_PA1_CFG2
#define BatteryEn_Voice_Button__PA__CFG3 CYREG_UDB_PA1_CFG3
#define BatteryEn_Voice_Button__PA__CFG4 CYREG_UDB_PA1_CFG4
#define BatteryEn_Voice_Button__PA__CFG5 CYREG_UDB_PA1_CFG5
#define BatteryEn_Voice_Button__PA__CFG6 CYREG_UDB_PA1_CFG6
#define BatteryEn_Voice_Button__PA__CFG7 CYREG_UDB_PA1_CFG7
#define BatteryEn_Voice_Button__PA__CFG8 CYREG_UDB_PA1_CFG8
#define BatteryEn_Voice_Button__PA__CFG9 CYREG_UDB_PA1_CFG9
#define BatteryEn_Voice_Button__PC CYREG_GPIO_PRT1_PC
#define BatteryEn_Voice_Button__PC2 CYREG_GPIO_PRT1_PC2
#define BatteryEn_Voice_Button__PORT 1u
#define BatteryEn_Voice_Button__PS CYREG_GPIO_PRT1_PS
#define BatteryEn_Voice_Button__SHIFT 7

/* Motion_Sensor_Interrupt */
#define Motion_Sensor_Interrupt__INTC_CLR_EN_REG CYREG_CM0_ICER
#define Motion_Sensor_Interrupt__INTC_CLR_PD_REG CYREG_CM0_ICPR
#define Motion_Sensor_Interrupt__INTC_MASK 0x04u
#define Motion_Sensor_Interrupt__INTC_NUMBER 2u
#define Motion_Sensor_Interrupt__INTC_PRIOR_MASK 0xC00000u
#define Motion_Sensor_Interrupt__INTC_PRIOR_NUM 3u
#define Motion_Sensor_Interrupt__INTC_PRIOR_REG CYREG_CM0_IPR0
#define Motion_Sensor_Interrupt__INTC_SET_EN_REG CYREG_CM0_ISER
#define Motion_Sensor_Interrupt__INTC_SET_PD_REG CYREG_CM0_ISPR

/* Motion_Sensor_Interrupt_Pin */
#define Motion_Sensor_Interrupt_Pin__0__DR CYREG_GPIO_PRT0_DR
#define Motion_Sensor_Interrupt_Pin__0__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define Motion_Sensor_Interrupt_Pin__0__DR_INV CYREG_GPIO_PRT0_DR_INV
#define Motion_Sensor_Interrupt_Pin__0__DR_SET CYREG_GPIO_PRT0_DR_SET
#define Motion_Sensor_Interrupt_Pin__0__HSIOM CYREG_HSIOM_PORT_SEL0
#define Motion_Sensor_Interrupt_Pin__0__HSIOM_MASK 0x00000F00u
#define Motion_Sensor_Interrupt_Pin__0__HSIOM_SHIFT 8u
#define Motion_Sensor_Interrupt_Pin__0__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_Interrupt_Pin__0__INTR CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_Interrupt_Pin__0__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_Interrupt_Pin__0__INTSTAT CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_Interrupt_Pin__0__MASK 0x04u
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG0 CYREG_UDB_PA0_CFG0
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG1 CYREG_UDB_PA0_CFG1
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG10 CYREG_UDB_PA0_CFG10
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG11 CYREG_UDB_PA0_CFG11
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG12 CYREG_UDB_PA0_CFG12
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG13 CYREG_UDB_PA0_CFG13
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG14 CYREG_UDB_PA0_CFG14
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG2 CYREG_UDB_PA0_CFG2
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG3 CYREG_UDB_PA0_CFG3
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG4 CYREG_UDB_PA0_CFG4
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG5 CYREG_UDB_PA0_CFG5
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG6 CYREG_UDB_PA0_CFG6
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG7 CYREG_UDB_PA0_CFG7
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG8 CYREG_UDB_PA0_CFG8
#define Motion_Sensor_Interrupt_Pin__0__PA__CFG9 CYREG_UDB_PA0_CFG9
#define Motion_Sensor_Interrupt_Pin__0__PC CYREG_GPIO_PRT0_PC
#define Motion_Sensor_Interrupt_Pin__0__PC2 CYREG_GPIO_PRT0_PC2
#define Motion_Sensor_Interrupt_Pin__0__PORT 0u
#define Motion_Sensor_Interrupt_Pin__0__PS CYREG_GPIO_PRT0_PS
#define Motion_Sensor_Interrupt_Pin__0__SHIFT 2
#define Motion_Sensor_Interrupt_Pin__DR CYREG_GPIO_PRT0_DR
#define Motion_Sensor_Interrupt_Pin__DR_CLR CYREG_GPIO_PRT0_DR_CLR
#define Motion_Sensor_Interrupt_Pin__DR_INV CYREG_GPIO_PRT0_DR_INV
#define Motion_Sensor_Interrupt_Pin__DR_SET CYREG_GPIO_PRT0_DR_SET
#define Motion_Sensor_Interrupt_Pin__INTCFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_Interrupt_Pin__INTR CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_Interrupt_Pin__INTR_CFG CYREG_GPIO_PRT0_INTR_CFG
#define Motion_Sensor_Interrupt_Pin__INTSTAT CYREG_GPIO_PRT0_INTR
#define Motion_Sensor_Interrupt_Pin__MASK 0x04u
#define Motion_Sensor_Interrupt_Pin__PA__CFG0 CYREG_UDB_PA0_CFG0
#define Motion_Sensor_Interrupt_Pin__PA__CFG1 CYREG_UDB_PA0_CFG1
#define Motion_Sensor_Interrupt_Pin__PA__CFG10 CYREG_UDB_PA0_CFG10
#define Motion_Sensor_Interrupt_Pin__PA__CFG11 CYREG_UDB_PA0_CFG11
#define Motion_Sensor_Interrupt_Pin__PA__CFG12 CYREG_UDB_PA0_CFG12
#define Motion_Sensor_Interrupt_Pin__PA__CFG13 CYREG_UDB_PA0_CFG13
#define Motion_Sensor_Interrupt_Pin__PA__CFG14 CYREG_UDB_PA0_CFG14
#define Motion_Sensor_Interrupt_Pin__PA__CFG2 CYREG_UDB_PA0_CFG2
#define Motion_Sensor_Interrupt_Pin__PA__CFG3 CYREG_UDB_PA0_CFG3
#define Motion_Sensor_Interrupt_Pin__PA__CFG4 CYREG_UDB_PA0_CFG4
#define Motion_Sensor_Interrupt_Pin__PA__CFG5 CYREG_UDB_PA0_CFG5
#define Motion_Sensor_Interrupt_Pin__PA__CFG6 CYREG_UDB_PA0_CFG6
#define Motion_Sensor_Interrupt_Pin__PA__CFG7 CYREG_UDB_PA0_CFG7
#define Motion_Sensor_Interrupt_Pin__PA__CFG8 CYREG_UDB_PA0_CFG8
#define Motion_Sensor_Interrupt_Pin__PA__CFG9 CYREG_UDB_PA0_CFG9
#define Motion_Sensor_Interrupt_Pin__PC CYREG_GPIO_PRT0_PC
#define Motion_Sensor_Interrupt_Pin__PC2 CYREG_GPIO_PRT0_PC2
#define Motion_Sensor_Interrupt_Pin__PORT 0u
#define Motion_Sensor_Interrupt_Pin__PS CYREG_GPIO_PRT0_PS
#define Motion_Sensor_Interrupt_Pin__SHIFT 2

/* Miscellaneous */
#define CY_PROJECT_NAME "CY5672_Remote_Control"
#define CY_VERSION "PSoC Creator  3.3 CP2"
#define CYDEV_BCLK__HFCLK__HZ 24000000U
#define CYDEV_BCLK__HFCLK__KHZ 24000U
#define CYDEV_BCLK__HFCLK__MHZ 24U
#define CYDEV_BCLK__SYSCLK__HZ 24000000U
#define CYDEV_BCLK__SYSCLK__KHZ 24000U
#define CYDEV_BCLK__SYSCLK__MHZ 24U
#define CYDEV_CHIP_DIE_LEOPARD 1u
#define CYDEV_CHIP_DIE_PANTHER 18u
#define CYDEV_CHIP_DIE_PSOC4A 10u
#define CYDEV_CHIP_DIE_PSOC5LP 17u
#define CYDEV_CHIP_DIE_TMA4 2u
#define CYDEV_CHIP_DIE_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_PSOC3 1u
#define CYDEV_CHIP_FAMILY_PSOC4 2u
#define CYDEV_CHIP_FAMILY_PSOC5 3u
#define CYDEV_CHIP_FAMILY_UNKNOWN 0u
#define CYDEV_CHIP_FAMILY_USED CYDEV_CHIP_FAMILY_PSOC4
#define CYDEV_CHIP_JTAG_ID 0x0E34119Eu
#define CYDEV_CHIP_MEMBER_3A 1u
#define CYDEV_CHIP_MEMBER_4A 10u
#define CYDEV_CHIP_MEMBER_4C 15u
#define CYDEV_CHIP_MEMBER_4D 6u
#define CYDEV_CHIP_MEMBER_4E 4u
#define CYDEV_CHIP_MEMBER_4F 11u
#define CYDEV_CHIP_MEMBER_4G 2u
#define CYDEV_CHIP_MEMBER_4H 9u
#define CYDEV_CHIP_MEMBER_4I 14u
#define CYDEV_CHIP_MEMBER_4J 7u
#define CYDEV_CHIP_MEMBER_4K 8u
#define CYDEV_CHIP_MEMBER_4L 13u
#define CYDEV_CHIP_MEMBER_4M 12u
#define CYDEV_CHIP_MEMBER_4N 5u
#define CYDEV_CHIP_MEMBER_4U 3u
#define CYDEV_CHIP_MEMBER_5A 17u
#define CYDEV_CHIP_MEMBER_5B 16u
#define CYDEV_CHIP_MEMBER_UNKNOWN 0u
#define CYDEV_CHIP_MEMBER_USED CYDEV_CHIP_MEMBER_4F
#define CYDEV_CHIP_DIE_EXPECT CYDEV_CHIP_MEMBER_USED
#define CYDEV_CHIP_DIE_ACTUAL CYDEV_CHIP_DIE_EXPECT
#define CYDEV_CHIP_REV_LEOPARD_ES1 0u
#define CYDEV_CHIP_REV_LEOPARD_ES2 1u
#define CYDEV_CHIP_REV_LEOPARD_ES3 3u
#define CYDEV_CHIP_REV_LEOPARD_PRODUCTION 3u
#define CYDEV_CHIP_REV_PANTHER_ES0 0u
#define CYDEV_CHIP_REV_PANTHER_ES1 1u
#define CYDEV_CHIP_REV_PANTHER_PRODUCTION 1u
#define CYDEV_CHIP_REV_PSOC4A_ES0 17u
#define CYDEV_CHIP_REV_PSOC4A_PRODUCTION 17u
#define CYDEV_CHIP_REV_PSOC5LP_ES0 0u
#define CYDEV_CHIP_REV_PSOC5LP_PRODUCTION 0u
#define CYDEV_CHIP_REV_TMA4_ES 17u
#define CYDEV_CHIP_REV_TMA4_ES2 33u
#define CYDEV_CHIP_REV_TMA4_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_3A_ES1 0u
#define CYDEV_CHIP_REVISION_3A_ES2 1u
#define CYDEV_CHIP_REVISION_3A_ES3 3u
#define CYDEV_CHIP_REVISION_3A_PRODUCTION 3u
#define CYDEV_CHIP_REVISION_4A_ES0 17u
#define CYDEV_CHIP_REVISION_4A_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4C_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4D_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4E_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256DMA 0u
#define CYDEV_CHIP_REVISION_4F_PRODUCTION_256K 0u
#define CYDEV_CHIP_REVISION_4G_ES 17u
#define CYDEV_CHIP_REVISION_4G_ES2 33u
#define CYDEV_CHIP_REVISION_4G_PRODUCTION 17u
#define CYDEV_CHIP_REVISION_4H_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4I_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4J_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4K_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4L_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4M_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4N_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_4U_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_5A_ES0 0u
#define CYDEV_CHIP_REVISION_5A_ES1 1u
#define CYDEV_CHIP_REVISION_5A_PRODUCTION 1u
#define CYDEV_CHIP_REVISION_5B_ES0 0u
#define CYDEV_CHIP_REVISION_5B_PRODUCTION 0u
#define CYDEV_CHIP_REVISION_USED CYDEV_CHIP_REVISION_4F_PRODUCTION
#define CYDEV_CHIP_REV_EXPECT CYDEV_CHIP_REVISION_USED
#define CYDEV_CONFIG_READ_ACCELERATOR 1
#define CYDEV_CONFIG_UNUSED_IO_AllowButWarn 0
#define CYDEV_CONFIG_UNUSED_IO CYDEV_CONFIG_UNUSED_IO_AllowButWarn
#define CYDEV_CONFIG_UNUSED_IO_AllowWithInfo 1
#define CYDEV_CONFIG_UNUSED_IO_Disallowed 2
#define CYDEV_CONFIGURATION_COMPRESSED 1
#define CYDEV_CONFIGURATION_MODE_COMPRESSED 0
#define CYDEV_CONFIGURATION_MODE CYDEV_CONFIGURATION_MODE_COMPRESSED
#define CYDEV_CONFIGURATION_MODE_DMA 2
#define CYDEV_CONFIGURATION_MODE_UNCOMPRESSED 1
#define CYDEV_DEBUG_PROTECT_KILL 4
#define CYDEV_DEBUG_PROTECT_OPEN 1
#define CYDEV_DEBUG_PROTECT CYDEV_DEBUG_PROTECT_OPEN
#define CYDEV_DEBUG_PROTECT_PROTECTED 2
#define CYDEV_DEBUGGING_DPS_Disable 3
#define CYDEV_DEBUGGING_DPS CYDEV_DEBUGGING_DPS_Disable
#define CYDEV_DEBUGGING_DPS_SWD 2
#define CYDEV_DEBUGGING_ENABLE 0
#define CYDEV_DFT_SELECT_CLK0 10u
#define CYDEV_DFT_SELECT_CLK1 11u
#define CYDEV_HEAP_SIZE 0x80
#define CYDEV_IMO_TRIMMED_BY_USB 0u
#define CYDEV_IMO_TRIMMED_BY_WCO 0u
#define CYDEV_IS_EXPORTING_CODE 0
#define CYDEV_IS_IMPORTING_CODE 0
#define CYDEV_PROJ_TYPE 0
#define CYDEV_PROJ_TYPE_BOOTLOADER 1
#define CYDEV_PROJ_TYPE_LAUNCHER 5
#define CYDEV_PROJ_TYPE_LOADABLE 2
#define CYDEV_PROJ_TYPE_LOADABLEANDBOOTLOADER 4
#define CYDEV_PROJ_TYPE_MULTIAPPBOOTLOADER 3
#define CYDEV_PROJ_TYPE_STANDARD 0
#define CYDEV_STACK_SIZE 0x0800
#define CYDEV_USE_BUNDLED_CMSIS 1
#define CYDEV_VARIABLE_VDDA 1
#define CYDEV_VDDA 2.2
#define CYDEV_VDDA_MV 2200
#define CYDEV_VDDD 2.2
#define CYDEV_VDDD_MV 2200
#define CYDEV_VDDR 2.2
#define CYDEV_VDDR_MV 2200
#define CYDEV_WDT_GENERATE_ISR 0u
#define CYIPBLOCK_m0s8bless_VERSION 1
#define CYIPBLOCK_m0s8cpussv2_VERSION 1
#define CYIPBLOCK_m0s8csd_VERSION 1
#define CYIPBLOCK_m0s8ioss_VERSION 1
#define CYIPBLOCK_m0s8lcd_VERSION 2
#define CYIPBLOCK_m0s8lpcomp_VERSION 2
#define CYIPBLOCK_m0s8peri_VERSION 1
#define CYIPBLOCK_m0s8scb_VERSION 2
#define CYIPBLOCK_m0s8srssv2_VERSION 1
#define CYIPBLOCK_m0s8tcpwm_VERSION 2
#define CYIPBLOCK_m0s8udbif_VERSION 1
#define CYIPBLOCK_s8pass4al_VERSION 1
#define CYDEV_BOOTLOADER_ENABLE 0

#endif /* INCLUDED_CYFITTER_H */
